Received: by 2002:a25:d80d:0:0:0:0:0 with SMTP id p13csp162850ybg; Sat, 23 May 2020 10:15:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwtIT3ERnQakpj8lz9yGZjdzhG5P+GEO41e+sRAAISUS44f2ofKRUU0UfecWXsDqf0AKS4q X-Received: by 2002:a05:6402:6c1:: with SMTP id n1mr8005198edy.199.1590254101576; Sat, 23 May 2020 10:15:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1590254101; cv=none; d=google.com; s=arc-20160816; b=NK7LEB9tk4dq7986TG/KiiLtRQXxlX9P3v1wdi+Bjil2XY1dx0kvznWZQt7xL1kCyP M5yt84WoxS3CNgGZuxcq4aZylhMHEnbNpoFXucVuyEdj30zfqhzLkpskkVxnSpFzxOmK OqlwS8Q1f6Me2USHUtHQOnyvqibtuyD4gQUcU+oCBNPoasVS/xzRx6C7/NjRNywvFEvj OR+ceaznIfehajgGU6CKwQ1yKvEJPUwqqNoKKIxZkCbHKWQULCxWh5XwLw6Vi97+v8ib WNZ3rvqX0YmOPzHAU10OzDZGG9rmjy5B0dFn1BJHiWs5yNqUWldiWeuap9N/wQMG9SQr U8Hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dmarc-filter:dkim-signature; bh=Xa/qM4zqWRu1/eInpOYfgqH291JWzSNfqUyeAVg2f5M=; b=gI6VGGAKHWLXC7XQrucILbWl5pM3PqWgu63FpyvdcJF5g0hsqVFdEdWRx2q0VCijzo g27e8lNm0tdIXw1LfGaHdspXXG0/A8Nr2gT+fJP93I5oV+/pzOjRwnr1nyOY9gCBAfpP cha8VPxbsGdb/DQwyy9UVYNXDJPuv9PvmFILC2vAjkcgKldLY3CQALoXGg7iGh3r9nSM POfCnGUXrPBzYyejSWKUfVtzoM5RUSN6qAS+8kTpLW50PFd+6JB+FnCh6qFQ8kONi7Hm KsPy0tRprA2B2UmuaTokv++SnAkpwxYQUdWpTonWr5v5TB+fkXJ6ekiWBbtYELqc0w1H shhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@mg.codeaurora.org header.s=smtp header.b=UOARDfBh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id sa8si6756012ejb.222.2020.05.23.10.14.39; Sat, 23 May 2020 10:15:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=fail header.i=@mg.codeaurora.org header.s=smtp header.b=UOARDfBh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388082AbgEWRMC (ORCPT + 99 others); Sat, 23 May 2020 13:12:02 -0400 Received: from mail26.static.mailgun.info ([104.130.122.26]:27799 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388032AbgEWRL7 (ORCPT ); Sat, 23 May 2020 13:11:59 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1590253919; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=Xa/qM4zqWRu1/eInpOYfgqH291JWzSNfqUyeAVg2f5M=; b=UOARDfBh/lMo9PGQ9otxyowYQqvS0HJ0uPbdsyQtWj9mpTQUjzuO3EVrwcc+n+1l4jR/dvSh 35IeHFBqL7MLjz6XqBLJ5VAK7ymIJ6vOwvSXx5yfZ0tDGNefA4PabWbii1UT7hnlc2uGQ3mo q/0ZzU/2rjRUyqdX1XFceNlgtjE= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5ec95955.7fbc61f829d0-smtp-out-n05; Sat, 23 May 2020 17:11:49 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 42AB3C43391; Sat, 23 May 2020 17:11:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mkshah-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mkshah) by smtp.codeaurora.org (Postfix) with ESMTPSA id A9FA1C433CB; Sat, 23 May 2020 17:11:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A9FA1C433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=mkshah@codeaurora.org From: Maulik Shah To: bjorn.andersson@linaro.org, maz@kernel.org, linus.walleij@linaro.org, swboyd@chromium.org, evgreen@chromium.org, mka@chromium.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, agross@kernel.org, tglx@linutronix.de, jason@lakedaemon.net, dianders@chromium.org, rnayak@codeaurora.org, ilina@codeaurora.org, lsrao@codeaurora.org, Maulik Shah Subject: [PATCH v2 4/4] irqchip: qcom-pdc: Introduce irq_set_wake call Date: Sat, 23 May 2020 22:41:13 +0530 Message-Id: <1590253873-11556-5-git-send-email-mkshah@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590253873-11556-1-git-send-email-mkshah@codeaurora.org> References: <1590253873-11556-1-git-send-email-mkshah@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove irq_disable callback to allow lazy disable for pdc interrupts. Add irq_set_wake callback that unmask interrupt in HW when drivers mark interrupt for wakeup. Interrupt will be cleared in HW during lazy disable if its not marked for wakeup. Signed-off-by: Maulik Shah --- drivers/irqchip/qcom-pdc.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 6ae9e1f..f7c0662 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -36,6 +36,7 @@ struct pdc_pin_region { u32 cnt; }; +DECLARE_BITMAP(pdc_wake_irqs, PDC_MAX_IRQS); static DEFINE_RAW_SPINLOCK(pdc_lock); static void __iomem *pdc_base; static struct pdc_pin_region *pdc_region; @@ -87,22 +88,20 @@ static void pdc_enable_intr(struct irq_data *d, bool on) raw_spin_unlock(&pdc_lock); } -static void qcom_pdc_gic_disable(struct irq_data *d) +static int qcom_pdc_gic_set_wake(struct irq_data *d, unsigned int on) { if (d->hwirq == GPIO_NO_WAKE_IRQ) - return; - - pdc_enable_intr(d, false); - irq_chip_disable_parent(d); -} + return 0; -static void qcom_pdc_gic_enable(struct irq_data *d) -{ - if (d->hwirq == GPIO_NO_WAKE_IRQ) - return; + if (on) { + pdc_enable_intr(d, true); + irq_chip_enable_parent(d); + set_bit(d->hwirq, pdc_wake_irqs); + } else { + clear_bit(d->hwirq, pdc_wake_irqs); + } - pdc_enable_intr(d, true); - irq_chip_enable_parent(d); + return irq_chip_set_wake_parent(d, on); } static void qcom_pdc_gic_mask(struct irq_data *d) @@ -110,6 +109,9 @@ static void qcom_pdc_gic_mask(struct irq_data *d) if (d->hwirq == GPIO_NO_WAKE_IRQ) return; + if (!test_bit(d->hwirq, pdc_wake_irqs)) + pdc_enable_intr(d, false); + irq_chip_mask_parent(d); } @@ -118,6 +120,7 @@ static void qcom_pdc_gic_unmask(struct irq_data *d) if (d->hwirq == GPIO_NO_WAKE_IRQ) return; + pdc_enable_intr(d, true); irq_chip_unmask_parent(d); } @@ -197,15 +200,13 @@ static struct irq_chip qcom_pdc_gic_chip = { .irq_eoi = irq_chip_eoi_parent, .irq_mask = qcom_pdc_gic_mask, .irq_unmask = qcom_pdc_gic_unmask, - .irq_disable = qcom_pdc_gic_disable, - .irq_enable = qcom_pdc_gic_enable, .irq_get_irqchip_state = qcom_pdc_gic_get_irqchip_state, .irq_set_irqchip_state = qcom_pdc_gic_set_irqchip_state, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_set_type = qcom_pdc_gic_set_type, + .irq_set_wake = qcom_pdc_gic_set_wake, .flags = IRQCHIP_MASK_ON_SUSPEND | - IRQCHIP_SET_TYPE_MASKED | - IRQCHIP_SKIP_SET_WAKE, + IRQCHIP_SET_TYPE_MASKED, .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, .irq_set_affinity = irq_chip_set_affinity_parent, }; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation