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[23.128.96.18]) by mx.google.com with ESMTP id r23si8976232edl.531.2020.05.24.20.43.19; Sun, 24 May 2020 20:43:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=C9orZv3P; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388771AbgEYDlW (ORCPT + 99 others); Sun, 24 May 2020 23:41:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388397AbgEYDlU (ORCPT ); Sun, 24 May 2020 23:41:20 -0400 Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BCE5C061A0E; Sun, 24 May 2020 20:41:20 -0700 (PDT) Received: by mail-pf1-x443.google.com with SMTP id z64so3759197pfb.1; Sun, 24 May 2020 20:41:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GfRuA4swEZrmalrNdqlTpHmV2cl0sSIm4Vls/KHgpHc=; b=C9orZv3PrRkWTbASRFpQKn/pleNM+1/3gOo/xuhZgznu3IcNilHc8Su+UwIakTsz91 2TvBCU3YPoy26Rygihm6Kv//TnN5XpTwHgMb1v9w9qqjX+9pMWW7XAs52DrPEwF8Bkeu yjvHuH9XryCRAy7Peupmnit1pJb152K2dP2h4x9tJ2AdIJ8YNBRU/uR6DIt1sf/8cf88 FKExZpKs3E7RbDcnnETBi7n6p7o8Z3Lbtn4hListwo6bga+Fve2TqicJXlXRk1S3QQa+ j6HmYfu6d8de1hUQqAt9hV5p7d3NxTSbq7/PObDmhPaR+sfq8yYSOtEuxHpRKzOFnNaA OliA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GfRuA4swEZrmalrNdqlTpHmV2cl0sSIm4Vls/KHgpHc=; b=nloIsucT1g0Q5uOEuDPAXn4zO3fkB7XC7jKujF7IqqVWlQxX+TEnJtLsRkgEv0PIm6 ntX1M+4ha9ycqRxBlrHRzFNJNa+K5bBVlXjzaBiKrIfyQIdloIjXc2Nwhdqp+Y7Tfrcj JgfRJlD/t4UyjlPrY8vFQ59kkvxvFM/ZYTBzPEgdfIdP562/jE6OL7m8RRCPz1i4xQh1 qOwbyZrHZ08urC5obEPV96DnFubiNhtSgdUI35fhKaiTZx/Zy1QNGncgYA3AJV7H81Q+ hgo4+Il0nWniJrEo+VIUstCHxFGAyftOLclJvlrSKNYOCf40apH6hgIQJ/VG0LKJQypv +HGA== X-Gm-Message-State: AOAM531abM5wWm1s5gz5OiENTAoTLGo7DpyETAXI8t0DpI0A5EU7QXPo JXes/qhAYBQPSb6zIpeg6Hs= X-Received: by 2002:aa7:84c6:: with SMTP id x6mr15337738pfn.46.1590378079666; Sun, 24 May 2020 20:41:19 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([103.206.191.44]) by smtp.gmail.com with ESMTPSA id 7sm11981695pfc.203.2020.05.24.20.41.15 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 May 2020 20:41:19 -0700 (PDT) From: dillon.minfei@gmail.com To: robh+dt@kernel.org, p.zabel@pengutronix.de, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, thierry.reding@gmail.com, sam@ravnborg.org, airlied@linux.ie, daniel@ffwll.ch, mturquette@baylibre.com, sboyd@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, dillon min Subject: [PATCH v5 2/8] ARM: dts: stm32: Add pin map for ltdc & spi5 on stm32f429-disco board Date: Mon, 25 May 2020 11:40:56 +0800 Message-Id: <1590378062-7965-3-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590378062-7965-1-git-send-email-dillon.minfei@gmail.com> References: <1590378062-7965-1-git-send-email-dillon.minfei@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: dillon min This patch adds the pin configuration for ltdc and spi5 controller on stm32f429-disco board. Signed-off-by: dillon min --- arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 67 ++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 392fa14..0eb107f 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -316,6 +316,73 @@ }; }; + ltdc_pins_f429_disco: ltdc-1 { + pins { + pinmux = , + /* LCD_HSYNC */ + , + /* LCD_VSYNC */ + , + /* LCD_CLK */ + , + /* LCD_R2 */ + , + /* LCD_R3 */ + , + /* LCD_R4 */ + , + /* LCD_R5 */ + , + /* LCD_R6*/ + , + /* LCD_R7 */ + , + /* LCD_G2 */ + , + /* LCD_G3 */ + , + /* LCD_G4 */ + , + /* LCD_B2 */ + , + /* LCD_B3*/ + , + /* LCD_G5 */ + , + /* LCD_G6 */ + , + /* LCD_G7 */ + , + /* LCD_B4 */ + , + /* LCD_B5 */ + , + /* LCD_B6 */ + , + /* LCD_B7 */ + ; + /* LCD_DE */ + slew-rate = <2>; + }; + }; + + spi5_pins: spi5-0 { + pins1 { + pinmux = , + /* SPI5_CLK */ + ; + /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; + /* SPI5_MISO */ + bias-disable; + }; + }; + dcmi_pins: dcmi-0 { pins { pinmux = , /* DCMI_HSYNC */ -- 2.7.4