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Subject: Re: [PATCH V3] pwm: tegra: dynamic clk freq configuration by PWM
 driver
From:   Jon Hunter <jonathanh@nvidia.com>
To:     Sandipan Patra <spatra@nvidia.com>, <treding@nvidia.com>,
        <u.kleine-koenig@pengutronix.de>
CC:     <bbasu@nvidia.com>, <ldewangan@nvidia.com>,
        <kyarlagadda@nvidia.com>, <linux-pwm@vger.kernel.org>,
        <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
References: <1590492335-25857-1-git-send-email-spatra@nvidia.com>
 <81646862-8cbd-95f1-506d-ea375e365d69@nvidia.com>
Message-ID: <c83f7297-f3da-2b49-bc1a-42bffe7faabd@nvidia.com>
Date:   Tue, 26 May 2020 13:44:40 +0100
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On 26/05/2020 13:05, Jon Hunter wrote:
> 
> On 26/05/2020 12:25, Sandipan Patra wrote:
>> Added support for dynamic clock freq configuration in pwm kernel driver.
>> Earlier the pwm driver used to cache boot time clock rate by pwm clock
>> parent during probe. Hence dynamically changing pwm frequency was not
>> possible for all the possible ranges. With this change, dynamic calculation
>> is enabled and it is able to set the requested period from sysfs knob
>> provided the value is supported by clock source.
>>
>> Changes mainly have 2 parts:
>>   - T186 and later chips [1]
>>   - T210 and prior chips [2]
>>
>> For [1] - Changes implemented to set pwm period dynamically and
>>           also checks added to allow only if requested period(ns) is
>>           below or equals to higher range.
>>
>> For [2] - Only checks if the requested period(ns) is below or equals
>>           to higher range defined by max clock limit. The limitation
>>           in T210 or prior chips are due to the reason of having only
>>           one pwm-controller supporting multiple channels. But later
>>           chips have multiple pwm controller instances each having
>> 	  single channel support.
>>
>> Signed-off-by: Sandipan Patra <spatra@nvidia.com>

...

>>  	/*
>> +	 *  Period in nano second has to be <= highest allowed period
>> +	 *  based on max clock rate of the pwm controller.
>> +	 *
>> +	 *  higher limit = max clock limit >> PWM_DUTY_WIDTH
>> +	 *  lower limit = min clock limit >> PWM_DUTY_WIDTH >> PWM_SCALE_WIDTH
> 
> Not sure why we mention the lower limit if we are not testing this
> condition. Does not appear to be relevant here. Or should we be checking
> this as well?

The above comment appears to be incorrect. Looking further at the code,
the code seems fine but the comment is confusing. I think you mean to
say that 'the period needs to be greater than the minimum period' and
that ...

 min period = max clock limit >> PWM_DUTY_WIDTH
 max period = min clock limit >> PWM_DUTY_WIDTH >> PWM_SCALE_WIDTH

> 
>> +	 */
>> +	if (period_ns < pc->min_period_ns)
>> +		return -EINVAL;
> 
> Something does not seem right here. If this is the highest allowed
> period, shouldn't this variable be called 'max_period_ns'?

Jon

-- 
nvpublic