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Tue, 26 May 2020 12:50:04 +0000 From: Bharat Kumar Gogada To: Rob Herring CC: "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "bhelgaas@google.com" , Ravikiran Gummaluri Subject: RE: [PATCH v7 1/2] PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port Thread-Topic: [PATCH v7 1/2] PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port Thread-Index: AQHWJGb/NJjMqJD1V0CRUShbSGSEjKixoPsAgAjDU4A= Date: Tue, 26 May 2020 12:50:04 +0000 Message-ID: References: <1588852716-23132-1-git-send-email-bharat.kumar.gogada@xilinx.com> <1588852716-23132-2-git-send-email-bharat.kumar.gogada@xilinx.com> <20200520222040.GA693614@bogus> In-Reply-To: <20200520222040.GA693614@bogus> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=xilinx.com; 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x-ms-exchange-antispam-messagedata: Put9BtCUdoGBk+xdorIaoDnRaxN+ORbuF82SPAolS+R5jhpGEVR82fvfpJJ9uF1sL7C74IzRPWegzdcxr6oJA6FazCekJyWHVDUnyje0HqV8+fN/CQGo8IXovws7+tAvHDeQdLTyA+UutzJJk+VNhn4REo8f9A+2RGvq8xXUezOo+0J9JgjbOrp/tImztX0eP2vI4lKaAbxKY9N3h8ZSMozRu/GOxF9Q8eeddtwkjjX9C/g34VrcD7ASbtvwgH1wm695v1X0+30aK96yonkNWa3vmpiNtaOSDFscX5Cvja6gnqNTccYVGiv+Oya5QXT2rfgNekQC2o4/KQs70QNX+vcd0wa7YU6uO9p9UbOPOHJTgQ2VL2jZVQ0id/P8zoVE7fzXYuStHIyVDbYEgFjk/Wz1sdcRDyLkHDNqyCijLmocQvccOlNyNEP++aTWHZ6USwCNSReIVOTVv40NvbU53HHf0fTA4PYBNQfhPbv0OCCUFCmGgxEPdc0Ccy18AU6l Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3a9f55ba-e419-4823-6473-08d801734fbe X-MS-Exchange-CrossTenant-originalarrivaltime: 26 May 2020 12:50:04.1910 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 2Ywvb9gqhyfZg1LaxNixN+/3PEVso+jxVshA2cQBBCG7cbIl8mB1/+uphbUbOR0a0jVOSq2HjWk2g1l8r/irVw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB4118 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Subject: Re: [PATCH v7 1/2] PCI: xilinx-cpm: Add YAML schemas for Versal > CPM Root Port >=20 > On Thu, May 07, 2020 at 05:28:35PM +0530, Bharat Kumar Gogada wrote: > > Add YAML schemas documentation for Versal CPM Root Port driver. > > > > Signed-off-by: Bharat Kumar Gogada > > --- > > .../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 105 > > +++++++++++++++++++++ > > 1 file changed, 105 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > new file mode 100644 > > index 0000000..5fc5c3f > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > @@ -0,0 +1,105 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: CPM Host Controller device tree for Xilinx Versal SoCs > > + > > +maintainers: > > + - Bharat Kumar Gogada > > + >=20 > allOf: > - $ref: /schemas/pci/pci-bus.yaml# >=20 > > +properties: > > + compatible: > > + const: xlnx,versal-cpm-host-1.00 > > + >=20 > > + "#address-cells": > > + const: 3 > > + > > + "#size-cells": > > + const: 2 >=20 > Can drop. >=20 > > + > > + reg: > > + items: > > + - description: Configuration space region and bridge registers. > > + - description: CPM system level control and status registers. > > + > > + reg-names: > > + items: > > + - const: cfg > > + - const: cpm_slcr > > + > > + interrupts: > > + maxItems: 1 > > + > > + msi-map: > > + description: > > + Maps a Requester ID to an MSI controller and associated MSI > sideband data. > > + > > + ranges: > > + maxItems: 2 > > + > > + "#interrupt-cells": > > + const: 1 > > + >=20 > > + interrupt-map-mask: > > + description: Standard PCI IRQ mapping properties. > > + > > + interrupt-map: > > + description: Standard PCI IRQ mapping properties. >=20 > Can drop these 2. >=20 > > + > > + interrupt_controller: >=20 > s/_/-/ >=20 > > + description: Interrupt controller child node. >=20 > type: object >=20 > And then need to describe all the properties under it too. Agreed, will describe properties under this child node. >=20 > > + > > + bus-range: > > + description: Range of bus numbers associated with this controller. >=20 > Can drop. >=20 > > + > > +required: > > + - compatible > > + - "#address-cells" > > + - "#size-cells" > > + - reg > > + - reg-names > > + - "#interrupt-cells" > > + - interrupts > > + - interrupt-parent > > + - interrupt-map > > + - interrupt-map-mask > > + - ranges > > + - bus-range > > + - msi-map >=20 > interrupt-controller node not required? Yes required, will add. >=20 > You can drop all the standard properties required in pci-bus.yaml (it's i= n > dtschema repo). Agreed, will drop. >=20 > > + > > +additionalProperties: false >=20 > This will need to be 'unevaluatedProperties: false' Thanks Rob, will fix these in next patch. Regards, Bharat >=20 > > + > > +examples: > > + - | > > + > > + versal { > > + #address-cells =3D <2>; > > + #size-cells =3D <2>; > > + cpm_pcie: pci@fca10000 { >=20 > pcie@... >=20 > > + compatible =3D "xlnx,versal-cpm-host-1.00"; > > + #address-cells =3D <3>; > > + #interrupt-cells =3D <1>; > > + #size-cells =3D <2>; > > + interrupts =3D <0 72 4>; > > + interrupt-parent =3D <&gic>; > > + interrupt-map-mask =3D <0 0 0 7>; > > + interrupt-map =3D <0 0 0 1 &pcie_intc_0 0>, > > + <0 0 0 2 &pcie_intc_0 1>, > > + <0 0 0 3 &pcie_intc_0 2>, > > + <0 0 0 4 &pcie_intc_0 3>; > > + bus-range =3D <0x00 0xff>; > > + ranges =3D <0x02000000 0x0 0xe0000000 0x0 0xe00= 00000 0x0 > 0x10000000>, > > + <0x43000000 0x80 0x00000000 0x80 0x000= 00000 0x0 > 0x80000000>; > > + msi-map =3D <0x0 &its_gic 0x0 0x10000>; > > + reg =3D <0x6 0x00000000 0x0 0x10000000>, > > + <0x0 0xfca10000 0x0 0x1000>; > > + reg-names =3D "cfg", "cpm_slcr"; > > + pcie_intc_0: interrupt_controller { > > + #address-cells =3D <0>; > > + #interrupt-cells =3D <1>; > > + interrupt-controller ; > > + }; > > + }; > > + }; > > -- > > 2.7.4 > >