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[23.128.96.18]) by mx.google.com with ESMTP id b5si1248979edu.182.2020.05.27.03.11.03; Wed, 27 May 2020 03:11:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=AcbMLcq+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387494AbgE0H1w (ORCPT + 99 others); Wed, 27 May 2020 03:27:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387405AbgE0H1v (ORCPT ); Wed, 27 May 2020 03:27:51 -0400 Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75ADBC03E97A; Wed, 27 May 2020 00:27:51 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id e11so10499687pfn.3; Wed, 27 May 2020 00:27:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3vUDSkp2rIRsyDWaQXlzdhkNXO48Q97985UUzAKneWQ=; b=AcbMLcq+gvdqJHFMAqIMip5RDOWtBG/2xVj6NMsQKpaoQojhzqFDwqdvqVoOwzB5Zr WcQuPzddk+kzGJvHz0WrluPPHJf8xlPg4ZCEEnASD0oMJVduLHeXSIaPwAiROQlWu8mQ KbPNzhA+31VVCvYE64GHl98FvW4qxS+scg8kcSlQQwnpcHWzjHQtGwCGtY7Pkg5W2uiN uK84MScZhZLntr2s4s0f/VToWnGFzHoPOXawK73jPR1XRLHfGd3C626Gz78uBxzTLAr8 yrb5pvGBdloV4joyzvoVmuGjYhdc2L9dn/yFbviXjYbWcFNqYoTo0Xdl6hnAHowfFXg6 EvFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3vUDSkp2rIRsyDWaQXlzdhkNXO48Q97985UUzAKneWQ=; b=pCUTzUAtIJRRuRYkx0qFOA9FFAt5+PHe1QgrU8ppQ7lwEWIo/9Y+HzLFXfOPvET4nF +s+WiiZPcVpFXPq9tdl0PHB83ALSRRKh1aLija2cVP8iGyTetUiNEmBL0hAGuDYcR+tk f0vf7vzdO4rgMKlwr9gIQI4uSHe18AQ1SmcROXlRmYs+w5XIyuQ8pd5gDpmEbCVgJGOp d10dojiuanF5rvHTysNv8/4b9axEOO/1bAszpkEIJhda/yS0PSPO0RJYlSOYx7XurFhc I89hqLOrygvPPBzFxzalJIQ/VIgPDMeWilJzLYVZHNEfosMWcMfz/G/fK0mkFkgDGVF4 nvkg== X-Gm-Message-State: AOAM532GjeSDICsD4WEyc/45nUJJGRERD5Sl01TnZKukn9iGufUTGeBd Zay7c6ll4z7VM0UhOTHHVB0= X-Received: by 2002:a63:e804:: with SMTP id s4mr2782856pgh.260.1590564471078; Wed, 27 May 2020 00:27:51 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([103.206.191.44]) by smtp.gmail.com with ESMTPSA id q201sm1371842pfq.40.2020.05.27.00.27.46 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 May 2020 00:27:50 -0700 (PDT) From: dillon.minfei@gmail.com To: robh+dt@kernel.org, p.zabel@pengutronix.de, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, thierry.reding@gmail.com, sam@ravnborg.org, airlied@linux.ie, daniel@ffwll.ch, mturquette@baylibre.com, sboyd@kernel.org, andy.shevchenko@gmail.com, noralf@tronnes.org, linus.walleij@linaro.org, broonie@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, dillonhua@gmail.com, dillon min Subject: [PATCH v6 2/9] ARM: dts: stm32: Add pin map for ltdc & spi5 on stm32f429-disco board Date: Wed, 27 May 2020 15:27:26 +0800 Message-Id: <1590564453-24499-3-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590564453-24499-1-git-send-email-dillon.minfei@gmail.com> References: <1590564453-24499-1-git-send-email-dillon.minfei@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: dillon min This patch adds the pin configuration for ltdc and spi5 controller on stm32f429-disco board. Signed-off-by: dillon min --- arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 67 ++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 392fa143ce07..0eb107f968cd 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -316,6 +316,73 @@ }; }; + ltdc_pins_f429_disco: ltdc-1 { + pins { + pinmux = , + /* LCD_HSYNC */ + , + /* LCD_VSYNC */ + , + /* LCD_CLK */ + , + /* LCD_R2 */ + , + /* LCD_R3 */ + , + /* LCD_R4 */ + , + /* LCD_R5 */ + , + /* LCD_R6*/ + , + /* LCD_R7 */ + , + /* LCD_G2 */ + , + /* LCD_G3 */ + , + /* LCD_G4 */ + , + /* LCD_B2 */ + , + /* LCD_B3*/ + , + /* LCD_G5 */ + , + /* LCD_G6 */ + , + /* LCD_G7 */ + , + /* LCD_B4 */ + , + /* LCD_B5 */ + , + /* LCD_B6 */ + , + /* LCD_B7 */ + ; + /* LCD_DE */ + slew-rate = <2>; + }; + }; + + spi5_pins: spi5-0 { + pins1 { + pinmux = , + /* SPI5_CLK */ + ; + /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; + /* SPI5_MISO */ + bias-disable; + }; + }; + dcmi_pins: dcmi-0 { pins { pinmux = , /* DCMI_HSYNC */ -- 2.7.4