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[23.128.96.18]) by mx.google.com with ESMTP id n13si2240052edv.140.2020.05.27.11.59.44; Wed, 27 May 2020 12:00:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@cerno.tech header.s=fm2 header.b=TwnzvMlZ; dkim=pass header.i=@messagingengine.com header.s=fm2 header.b=Je62+51A; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=cerno.tech Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725766AbgE0PuW (ORCPT + 98 others); Wed, 27 May 2020 11:50:22 -0400 Received: from new1-smtp.messagingengine.com ([66.111.4.221]:48669 "EHLO new1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390209AbgE0PuG (ORCPT ); Wed, 27 May 2020 11:50:06 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.nyi.internal (Postfix) with ESMTP id 7DA7058204A; Wed, 27 May 2020 11:50:05 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Wed, 27 May 2020 11:50:05 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=kW7Ps2oNt5lvy Y7OIGFl8oRdikr/7SrdDhAW5AmKu+k=; b=TwnzvMlZ0TBGmflCytGhjo05+Use7 Ypbik81BG0rOD8nStJ6uSq2ygD/BsFTE9vCRBr2vSLChYP8s4+JhIZbvO6bFdogJ BKN0LqQWD9heIbaRt9uC0/N8rrtVCUFwaMgeWGMi3vyD2kGWiegHf9ObCBoyzfLx 4iUM/eOGAACSTUc7CPDwfCMQVMBV8sPUFBToxOaSkrGzCg6o8JCo3+yKs/LQSOYl cyiNM7oSV59bryOdN/N7KVEd9/EssWDVU/RdZkZxMIgFC+mG52VTsfF+5XJu/hcp Sb0ZXFvg9IFWOO2UbAP92/ML6hwZ0LHSNl1xA4sbW3Lbv9QL9gb8YdMqA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=kW7Ps2oNt5lvyY7OIGFl8oRdikr/7SrdDhAW5AmKu+k=; b=Je62+51A IohyO1Mw8jMyhRMi3EUO4o3Y2/XO8ruUSufwaLHAYreEcj4jvhgWBzWsY47lBR2c fP9VvsjEVNsueKvvAzpWoESy3y1bWQ53beCqzTPYA8iPDraQ9ztabo3OFYlTM1Vf s771WamtAr6E9+fQAVoPavr8m3S2hBsmbCb8E1oZDV3mWQwfGQ20wc3/mHhRxFCx nredSEDz1hYnEuZDx+1n37Cw0KcSZvn8xLGBunAKk/0NcPV2av+PPgxeAdZrOVwb VOVefhesbPbL/qyYxns6vyy5/Tx3xcQxsS0H/uif105NPJrxXW2IFjOcpACfw05T Jj0Izec4iP/agw== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduhedruddvgedgkeegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeforgigihhm vgcutfhiphgrrhguuceomhgrgihimhgvsegtvghrnhhordhtvggthheqnecuggftrfgrth htvghrnhepvdekleevfeffkeejhfffueelteelfeduieefheduudfggffhhfffheevveeh hedvnecukfhppeeltddrkeelrdeikedrjeeinecuvehluhhsthgvrhfuihiivgepuddune curfgrrhgrmhepmhgrihhlfhhrohhmpehmrgigihhmvgestggvrhhnohdrthgvtghh X-ME-Proxy: Received: from localhost (lfbn-tou-1-1502-76.w90-89.abo.wanadoo.fr [90.89.68.76]) by mail.messagingengine.com (Postfix) with ESMTPA id 1BA86328005A; Wed, 27 May 2020 11:50:05 -0400 (EDT) From: Maxime Ripard To: Nicolas Saenz Julienne , Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tim Gover , Phil Elwell , Maxime Ripard Subject: [PATCH v3 030/105] drm/vc4: crtc: Rename HVS channel to output Date: Wed, 27 May 2020 17:48:00 +0200 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In vc5, the HVS has 6 outputs and 3 FIFOs (or channels), with pixelvalves each being assigned to a given output, but each output can then be muxed to feed from multiple FIFOs. Since vc4 had that entirely static, both were probably equivalent, but since that changes, let's rename hvs_channel to hvs_output in the vc4_crtc_data, since a pixelvalve is really connected to an output, and not to a FIFO. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 10 +++++----- drivers/gpu/drm/vc4/vc4_drv.h | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index d58f881649d5..14e3a962d8a7 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -1056,7 +1056,7 @@ static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { }; static const struct vc4_crtc_data bcm2835_pv0_data = { - .hvs_channel = 0, + .hvs_output = 0, .debugfs_name = "crtc0_regs", .pixels_per_clock = 1, .encoder_types = { @@ -1066,7 +1066,7 @@ static const struct vc4_crtc_data bcm2835_pv0_data = { }; static const struct vc4_crtc_data bcm2835_pv1_data = { - .hvs_channel = 2, + .hvs_output = 2, .debugfs_name = "crtc1_regs", .pixels_per_clock = 1, .encoder_types = { @@ -1076,7 +1076,7 @@ static const struct vc4_crtc_data bcm2835_pv1_data = { }; static const struct vc4_crtc_data bcm2835_pv2_data = { - .hvs_channel = 1, + .hvs_output = 1, .debugfs_name = "crtc2_regs", .pixels_per_clock = 1, .encoder_types = { @@ -1105,7 +1105,7 @@ static void vc4_set_crtc_possible_masks(struct drm_device *drm, int i; /* HVS FIFO2 can feed the TXP IP. */ - if (crtc_data->hvs_channel == 2 && + if (crtc_data->hvs_output == 2 && encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) { encoder->possible_crtcs |= drm_crtc_mask(crtc); continue; @@ -1167,7 +1167,7 @@ static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, &vc4_crtc_funcs, NULL); drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs); - vc4_crtc->channel = vc4_crtc->data->hvs_channel; + vc4_crtc->channel = vc4_crtc->data->hvs_output; drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index 6c4b78b71446..9d120aae4af9 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -450,8 +450,8 @@ to_vc4_encoder(struct drm_encoder *encoder) } struct vc4_crtc_data { - /* Which channel of the HVS this pixelvalve sources from. */ - int hvs_channel; + /* Which output of the HVS this pixelvalve sources from. */ + int hvs_output; /* Number of pixels output per clock period */ u8 pixels_per_clock; -- git-series 0.9.1