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[23.128.96.18]) by mx.google.com with ESMTP id oe20si2468336ejb.135.2020.05.27.12.00.03; Wed, 27 May 2020 12:00:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@cerno.tech header.s=fm2 header.b="a/Xn4+11"; dkim=pass header.i=@messagingengine.com header.s=fm2 header.b="Hiq/c1jp"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=cerno.tech Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730640AbgE0Pu5 (ORCPT + 98 others); Wed, 27 May 2020 11:50:57 -0400 Received: from new1-smtp.messagingengine.com ([66.111.4.221]:34895 "EHLO new1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730571AbgE0Pue (ORCPT ); Wed, 27 May 2020 11:50:34 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.nyi.internal (Postfix) with ESMTP id 82BC6582096; Wed, 27 May 2020 11:50:33 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Wed, 27 May 2020 11:50:33 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=oDKZIgoeG+vnD EfqXcJAda79bnMM+UMDrK/U0Onwb1w=; b=a/Xn4+11C4fXDUvHzBoeRoGWVulPI 0kTzhNDJMeaZQHurBlMtx1HneHExI+Khp5kAU/5+rzL9ZZfFPGLEA2eUJaLO0LZO fudOW7Uw5Fpe57Ml2AfP9bYc31R7Zk7Ui6+4LZ8f7qBVE+zmoX2bxLf454En9ncK +X7sWUuuRYtY2zE/uHOTxPjI25VDNNKy2tUgysPGjlTjwolTcvbyNcd6/A/BCczF YEwK5fQuxV+F7Ww0sE+d+hv/Ug/rc1JsSPAl+Ly2ic94Wx9ljXnlp+GqnKmjtV9k 7NKwYb3o7jSZIfzRi1fbdoapSdpVGI6MuMQZNaaysp1rJbeSbwDzTI2wA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=oDKZIgoeG+vnDEfqXcJAda79bnMM+UMDrK/U0Onwb1w=; b=Hiq/c1jp avrufbNjOhMZXDNJx3gYpXSZg6gHYKBQk3iGZ+PU8QLQgpaUOhhKK2FOpGzWIINY f/egZWG1uEgK7Nx9nnWOmJAFps/qIjo5P6lrI4Lb0cMIEBGpbEJwu8qfBfl3PzqQ qQKM67Cwr/ExRzofXxceHz9QejZ1V5Y9c+u/YF3YDynTmSdHLJHBkoVHP02YxHfN T974zTz1NLAK8S9r7N88ik/w++Y9JGeQ/WBfdOT+daG6BsKMxYi4UFLd+80RqCJd 1/0L90kG4OqUOLOp11WRA8gg/eORxVIwLZrMjBQWfAyPEUX1pcxXRLBRpAAgXABj hYQFt7ovkl7nOg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduhedruddvgedgkeegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeforgigihhm vgcutfhiphgrrhguuceomhgrgihimhgvsegtvghrnhhordhtvggthheqnecuggftrfgrth htvghrnhepvdekleevfeffkeejhfffueelteelfeduieefheduudfggffhhfffheevveeh hedvnecukfhppeeltddrkeelrdeikedrjeeinecuvehluhhsthgvrhfuihiivgepvdelne curfgrrhgrmhepmhgrihhlfhhrohhmpehmrgigihhmvgestggvrhhnohdrthgvtghh X-ME-Proxy: Received: from localhost (lfbn-tou-1-1502-76.w90-89.abo.wanadoo.fr [90.89.68.76]) by mail.messagingengine.com (Postfix) with ESMTPA id 32A7E3280060; Wed, 27 May 2020 11:50:33 -0400 (EDT) From: Maxime Ripard To: Nicolas Saenz Julienne , Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tim Gover , Phil Elwell , Maxime Ripard Subject: [PATCH v3 048/105] drm/vc4: crtc: Remove redundant pixelvalve reset Date: Wed, 27 May 2020 17:48:18 +0200 Message-Id: <0fa72666fcd0ad1d0c97f92310c60238715bbd59.1590594512.git-series.maxime@cerno.tech> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since we moved the pixelvalve configuration to atomic_enable, we're now first calling the function that resets the pixelvalve and then the one that configures it. However, the first thing the latter is doing is calling the reset function, meaning that we reset twice our pixelvalve. Let's remove the first call. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 08bd595f6a7c..3c9b0d684136 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -433,8 +433,6 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, require_hvs_enabled(dev); - vc4_crtc_pixelvalve_reset(crtc); - if (!vc4_state->feed_txp) vc4_crtc_config_pv(crtc); -- git-series 0.9.1