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Wed, 27 May 2020 10:54:36 -0700 Date: Wed, 27 May 2020 10:54:35 -0700 From: Hyun Kwon To: Laurent Pinchart Cc: Venkateshwar Rao Gannavarapu , Hyun Kwon , "dri-devel@lists.freedesktop.org" , "airlied@linux.ie" , "daniel@ffwll.ch" , "linux-kernel@vger.kernel.org" , Sandip Kothari Subject: Re: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem Message-ID: <20200527175435.GA26381@smtp.xilinx.com> References: <1587417656-48078-1-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> <1587417656-48078-3-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> <20200504184348.GA3095@smtp.xilinx.com> <20200524030813.GF6026@pendragon.ideasonboard.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20200524030813.GF6026@pendragon.ideasonboard.com> User-Agent: Mutt/1.5.24 (2015-08-30) X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapsmtpgw01;PTR:unknown-60-83.xilinx.com;CAT:NONE;SFTY:;SFS:(346002)(376002)(136003)(39860400002)(396003)(46966005)(6916009)(54906003)(70586007)(70206006)(81166007)(33656002)(356005)(82310400002)(316002)(83380400001)(426003)(5660300002)(336012)(44832011)(26005)(186003)(1076003)(47076004)(82740400003)(8676002)(9786002)(478600001)(2906002)(4326008)(8936002)(107886003);DIR:OUT;SFP:1101; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 815cecd2-ffcc-4ae5-587e-08d8026709b7 X-MS-TrafficTypeDiagnostic: MN2PR02MB6752: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-Forefront-PRVS: 04163EF38A X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1MWuiYcq7844ohiVS8uhW8hysCX4UI5LSPW2pQVJAn8PxW5P5+DML/896nYE/SlNodUa1QrTEsoU6ZWItawPGGQXoZxBYPdUJ0RaALZ0k0pGkmBi06qxfyqFCgAhbp7saRUnfHj2Yp4mcBeMqVE45+KnU1frCV9wq7Aa/5VGBskJNq3n0Shd4Ahd0ZlWYfkKRHRbvvjiqLE0r1WPSnGe9R/64cNK2riS3SOTr/PWU2Th745oELzNIIdfHY/wi4fazzqW2cVfsL/II+tFhQ9IRYu82l5GyosXeRXFVDYOXz6hQbLPVVwJ4aOkSoEDpxCgwAh9sheWEbK9dx2y4bw9cMewzFZU0mOQ9eN/fP1YQ+ZvY32KqGfgK7qTd2SKI8rUY63qZLj/Az+YmTzHYhWXPQ== X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2020 17:54:44.0742 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 815cecd2-ffcc-4ae5-587e-08d8026709b7 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB6752 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Laurent, On Sat, 2020-05-23 at 20:08:13 -0700, Laurent Pinchart wrote: > Hi GVRao, > > Thank you for the patch. > > On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote: > > On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote: > > > The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video > > > data from AXI-4 stream interface. > > > > > > It supports upto 4 lanes, optional register interface for the DPHY, > > > > I don't see the register interface for dphy support. > > I think the D-PHY should be supported through a PHY driver, as it seems > to be shared between different subsystems. > Right, if the logic is shared across subsystems. I can't tell if that's the case as the IP comes as a single block. Maybe GVRao can confirm. > > > multiple RGB color formats, command mode and video mode. > > > This is a MIPI-DSI host driver and provides DSI bus for panels. > > > This driver also helps to communicate with its panel using panel > > > framework. > > > > > > Signed-off-by: Venkateshwar Rao Gannavarapu > > > --- > > > drivers/gpu/drm/xlnx/Kconfig | 11 + > > > drivers/gpu/drm/xlnx/Makefile | 2 + > > > drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 ++++++++++++++++++++++++++++++++++++++++ > > Daniel Vetter has recently expressed his opiion that bridge drivers > should go to drivers/gpu/drm/bridge/. It would then be > drivers/gpu/drm/bridge/xlnx/. I don't have a strong opinion myself. > > > > 3 files changed, 768 insertions(+) > > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c > > > > > > diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig > > > index aa6cd88..73873cf 100644 > > > --- a/drivers/gpu/drm/xlnx/Kconfig > > > +++ b/drivers/gpu/drm/xlnx/Kconfig > > > @@ -11,3 +11,14 @@ config DRM_ZYNQMP_DPSUB > > > This is a DRM/KMS driver for ZynqMP DisplayPort controller. Choose > > > this option if you have a Xilinx ZynqMP SoC with DisplayPort > > > subsystem. > > > + > > > +config DRM_XLNX_DSI > > > + tristate "Xilinx DRM DSI Subsystem Driver" > > > + select DRM_MIPI_DSI > > > + select DRM_PANEL > > > + select DRM_PANEL_SIMPLE > > > + help > > > + This enables support for Xilinx MIPI-DSI. > > > > This sentence is not needed with below. Could you please rephrase the whole? > > > > > + This is a DRM/KMS driver for Xilinx programmable DSI controller. > > > + Choose this option if you have a Xilinx MIPI DSI-TX controller > > > + subsytem. > > > > These seem incorrectly indented. > > > > > diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile > > > index 2b844c6..b7ee6ef 100644 > > > --- a/drivers/gpu/drm/xlnx/Makefile > > > +++ b/drivers/gpu/drm/xlnx/Makefile > > > @@ -1,2 +1,4 @@ > > > zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o > > > obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o > > > + > > > +obj-$(CONFIG_DRM_XLNX_DSI) += xlnx_dsi.o > > > diff --git a/drivers/gpu/drm/xlnx/xlnx_dsi.c b/drivers/gpu/drm/xlnx/xlnx_dsi.c > > > new file mode 100644 > > > index 0000000..b8cae59 > > > --- /dev/null > > > +++ b/drivers/gpu/drm/xlnx/xlnx_dsi.c > > > @@ -0,0 +1,755 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +/* > > > + * Xilinx FPGA MIPI DSI Tx Controller driver > > > + * > > > + * Copyright (C) 2017 - 2019 Xilinx, Inc. > > > + * > > > + * Authors: > > > + * - Saurabh Sengar > > > + * - Venkateshwar Rao Gannavarapu > > > + */ > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +#include