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[23.128.96.18]) by mx.google.com with ESMTP id o10si3018994ejr.656.2020.05.27.18.39.02; Wed, 27 May 2020 18:39:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726487AbgE1BfW (ORCPT + 99 others); Wed, 27 May 2020 21:35:22 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:5294 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725747AbgE1BfV (ORCPT ); Wed, 27 May 2020 21:35:21 -0400 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 4A5E2CDD85FBA056B940; Thu, 28 May 2020 09:35:19 +0800 (CST) Received: from [127.0.0.1] (10.74.221.148) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.487.0; Thu, 28 May 2020 09:35:12 +0800 Subject: Re: [PATCH V1 RESEND 1/3] perf/imx_ddr: Add system PMU identifier for userspace To: John Garry , Will Deacon , "Rob Herring" References: <20200512073115.14177-1-qiangqing.zhang@nxp.com> <20200512073115.14177-2-qiangqing.zhang@nxp.com> <20200519185125.GB453195@bogus> <20200520073304.GA23534@willie-the-truck> <20200521130415.GB5949@willie-the-truck> <51aa7cbc-0ce2-b96d-b056-fcc6013ccecf@huawei.com> CC: Mark Rutland , , "Joakim Zhang" , "linux-kernel@vger.kernel.org" , NXP Linux Team , Shawn Guo , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" From: Shaokun Zhang Message-ID: <36a5bf0c-fcf5-ad74-b5ee-1b4502705aec@hisilicon.com> Date: Thu, 28 May 2020 09:35:13 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: <51aa7cbc-0ce2-b96d-b056-fcc6013ccecf@huawei.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.74.221.148] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 2020/5/27 22:34, John Garry wrote: >>>>> >>>>> I also really dislike this. What's the preferred way to identify the SoC >>>>> from userspace? >>>> >>>> /proc/cpuinfo? ;) >>> >>> The *SoC*! >>> >>>> For an non-firmware specific case, I'd say soc_device should be. I'd >>>> guess ACPI systems don't use it and for them it's dmidecode typically. >>>> The other problem I have with soc_device is it is optional. >>> >> >> Hi Will, >> >>> John -- what do you think about using soc_device to expose this information, >>> with ACPI systems using DMI data instead? >> >> Generally I don't think that DMI is reliable, and I saw this as the least preferred choice. I'm looking at the sysfs DMI info for my dev board, and I don't even see anything like a SoC identifier. >> >> As for the event_source device sysfs identifier file, it would not always contain effectively the same as the SoC ID. >> >> Certain PMUs which I'm interested in plan to have probe-able identification info available in future. >> > > BTW, Shaokun now tells me that the HiSi uncore PMU HW have such registers to identify the implementation. I didn't know. > Right, we have this register which shows the PMU version. Thanks, Shaokun > So we could add that identifier file for those PMUs as proof-of-concept, exposing that register. > > As for other PMUs which I'm interested in, again, future versions should have such registers to self-identify. > > So using something derived from the DT compat string would hopefully be the uncommon case. > > Cheers, > John > > . >