Received: by 2002:a25:ef43:0:0:0:0:0 with SMTP id w3csp99290ybm; Wed, 27 May 2020 20:41:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy4L2Fa/gSLEMpDRnlR07ctkiayDaBx7C5VMteatVzAURL0LmsE8OzczPS+bVV2lgVinUDk X-Received: by 2002:a17:906:bc55:: with SMTP id s21mr1203368ejv.21.1590637309189; Wed, 27 May 2020 20:41:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1590637309; cv=none; d=google.com; s=arc-20160816; b=uVmzSRzRba0xdyOeCTZFj6c/eLPFpjK5wBVlcRzyFih21EbaeKNkHJofNri9JeReN2 WoX1yJ+Nx8lxsJsEsxZNy6PamuL45LNpO8ylrY4JAZt7wJNXlCCQOpk/2aJMBhnBZe+Y F9HYYPZOuTCotoovUj53wQMMqiq47Cd6Dx6TkRB/sUgedt/oQmAyw7cdD5v15MoXbEmi 7mvrB/5O2omMBtRdW4UrlJAUTKJxphqG6mjU2+cWTsohpfc532XAl8QaQ76fciwvAW3y zkwhJdXxyNHGgk4E9zwIonr+mBlnSBB5fEPOAfPj34c3MIKUiCnXT6yT0Que7K3P3H09 VY6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=6XJyhOJHjSYfRdsoUlD4FmuYI7Lf75n5YDlDXT9ePBI=; b=0jHIdTOQoI4AKZOiRvABzuiZMMT/MtYJurRRWoaqCIuPpDbcGhV/ShZXUmW3lqX1Gl nwb7tcp5tCtsymY7Oul5J6va0KK+n7HBwyIt4eIvThuov+D+LttyPPg3xkY1pK9VVvFP JzuTMLQ9zrhNKO0zS7LgNkGgVdcmFns5KZqs64rOOkq6CqZyzMWmzVWEyr/pelnWP7VH PcopAbQCVfGyP2jybKRLhfKeaQ0rc3gCuFeNl4rmcxlesSne4kKd1SP6uyDDeQIeqekc /y5xlMI2A/XL6iTLMwh6OghoSEdTmo+S3GBcU5XNem8MjqUueWoM4fF9bOH44m9EQJLh JoPQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z23si3128397ejb.144.2020.05.27.20.41.26; Wed, 27 May 2020 20:41:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727016AbgE1Djo (ORCPT + 99 others); Wed, 27 May 2020 23:39:44 -0400 Received: from relay9-d.mail.gandi.net ([217.70.183.199]:42817 "EHLO relay9-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726530AbgE1Djo (ORCPT ); Wed, 27 May 2020 23:39:44 -0400 X-Originating-IP: 86.202.110.81 Received: from localhost (lfbn-lyo-1-15-81.w86-202.abo.wanadoo.fr [86.202.110.81]) (Authenticated sender: alexandre.belloni@bootlin.com) by relay9-d.mail.gandi.net (Postfix) with ESMTPSA id 0F3A8FF806; Thu, 28 May 2020 03:39:41 +0000 (UTC) Date: Thu, 28 May 2020 05:39:41 +0200 From: Alexandre Belloni To: Rob Herring Cc: Lars Povlsen , Guenter Roeck , SoC Team , Jean Delvare , Microchip Linux Driver Support , linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/3] arm64: dts: sparx5: Add hwmon temperature sensor Message-ID: <20200528033941.GQ3972@piout.net> References: <20200513134140.25357-1-lars.povlsen@microchip.com> <20200513134140.25357-3-lars.povlsen@microchip.com> <20200528022931.GA3238321@bogus> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200528022931.GA3238321@bogus> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob, On 27/05/2020 20:29:31-0600, Rob Herring wrote: > On Wed, May 13, 2020 at 03:41:39PM +0200, Lars Povlsen wrote: > > This adds a hwmon temperature node sensor to the Sparx5 SoC. > > > > Reviewed-by: Alexandre Belloni > > Signed-off-by: Lars Povlsen > > --- > > arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi > > index f09a49c41ce19..b5f2d088af30e 100644 > > --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi > > +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi > > @@ -233,5 +233,11 @@ i2c1: i2c@600103000 { > > clock-frequency = <100000>; > > clocks = <&ahb_clk>; > > }; > > + > > + tmon0: tmon@610508110 { > > + compatible = "microchip,sparx5-temp"; > > + reg = <0x6 0x10508110 0xc>; > > These nodes are all very odd with a couple of registers spread out at > randomish addresses. DT nodes should roughly correlate to h/w blocks, > not sets of registers for a driver like this seems to be. > The DT nodes correlates to HW block, this and the previous families of SoCs were designed with packed registers. There is no padding between HW block registers. -- Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com