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Subject: Re: [PATCH] clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src
To:     linux-kernel@vger.kernel.org
References: <20200528142205.44003-1-jeffrey.l.hugo@gmail.com>
From:   Jami Kettunen <jamipkettunen@gmail.com>
Message-ID: <e2d1f11d-9a16-a6be-6773-3f27afef2149@gmail.com>
Date:   Thu, 28 May 2020 18:36:52 +0300
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Tested-by: Jami Kettunen <jamipkettunen@gmail.com>

On 28.5.2020 17.22, Jeffrey Hugo wrote:
> ufs_unipro_core_clk_src is required to allow UFS to clock scale for power
> savings.
>
> Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver")
> Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
> ---
>   drivers/clk/qcom/gcc-msm8998.c               | 27 ++++++++++++++++++++
>   include/dt-bindings/clock/qcom,gcc-msm8998.h |  1 +
>   2 files changed, 28 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
> index df1d7056436c..9d7016bcd680 100644
> --- a/drivers/clk/qcom/gcc-msm8998.c
> +++ b/drivers/clk/qcom/gcc-msm8998.c
> @@ -1110,6 +1110,27 @@ static struct clk_rcg2 ufs_axi_clk_src = {
>   	},
>   };
>   
> +static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
> +	F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
> +	F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> +	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 ufs_unipro_core_clk_src = {
> +	.cmd_rcgr = 0x76028,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_ufs_unipro_core_clk_src,
> +	.clkr.hw.init = &(struct clk_init_data){
> +		.name = "ufs_unipro_core_clk_src",
> +		.parent_names = gcc_parent_names_0,
> +		.num_parents = 4,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
>   static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
>   	F(19200000, P_XO, 1, 0, 0),
>   	F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
> @@ -2549,6 +2570,11 @@ static struct clk_branch gcc_ufs_unipro_core_clk = {
>   		.enable_mask = BIT(0),
>   		.hw.init = &(struct clk_init_data){
>   			.name = "gcc_ufs_unipro_core_clk",
> +			.parent_names = (const char *[]){
> +				"ufs_unipro_core_clk_src",
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>   			.ops = &clk_branch2_ops,
>   		},
>   	},
> @@ -2904,6 +2930,7 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
>   	[SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
>   	[TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
>   	[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
> +	[UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
>   	[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
>   	[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
>   	[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
> diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h
> index 63e02dc32a0b..6a73a174f049 100644
> --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h
> +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h
> @@ -183,6 +183,7 @@
>   #define GCC_MSS_SNOC_AXI_CLK					174
>   #define GCC_MSS_MNOC_BIMC_AXI_CLK				175
>   #define GCC_BIMC_GFX_CLK					176
> +#define UFS_UNIPRO_CORE_CLK_SRC					177
>   
>   #define PCIE_0_GDSC						0
>   #define UFS_GDSC						1