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([2001:b07:6468:f312:b096:1b7:7695:e4f7]) by smtp.gmail.com with ESMTPSA id e6sm3010301wrx.80.2020.05.29.03.24.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 May 2020 03:24:00 -0700 (PDT) Subject: Re: [Qemu-devel PATCH] target/i386: define a new MSR based feature word - FEAT_PERF_CAPABILITIES To: Like Xu Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Richard Henderson , Eduardo Habkost , Marcelo Tosatti , qemu-devel@nongnu.org References: <20200529074347.124619-1-like.xu@linux.intel.com> <20200529074347.124619-5-like.xu@linux.intel.com> From: Paolo Bonzini Message-ID: <1aa68600-e48d-fa83-b2e2-b070a486afd4@redhat.com> Date: Fri, 29 May 2020 12:23:59 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20200529074347.124619-5-like.xu@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29/05/20 09:43, Like Xu wrote: > + if (!cpu->enable_pmu) { > + *ecx &= ~CPUID_EXT_PDCM; > + } > break; > case 2: > /* cache info: needed for Pentium Pro compatibility */ > @@ -6505,6 +6528,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) > } > } > > + if (kvm_enabled() && cpu->enable_pmu && > + (kvm_arch_get_supported_cpuid(kvm_state, 1, 0, R_ECX) & > + CPUID_EXT_PDCM)) { > + env->features[FEAT_1_ECX] |= CPUID_EXT_PDCM; > + } > + I'm dropping this hunk two hunks because it's going to break live migration with e.g. "-cpu IvyBridge,pmu=on". We will have to add PDCM by default only to future CPU models, but "-cpu host,pmu=on" will pick it up automatically. Paolo