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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200529175831.p4dphb5luymgapzx@wunner.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/29/20 10:58 AM, Lukas Wunner wrote: > On Fri, May 29, 2020 at 10:48:11AM -0700, Florian Fainelli wrote: >> On 5/29/20 10:47 AM, Lukas Wunner wrote: >>> On Thu, May 28, 2020 at 12:06:05PM -0700, Florian Fainelli wrote: >>>> Make sure we clear the FIFOs, stop the block, disable the clock and >>>> release the DMA channel. >>> >>> To what end? Why is this change necessary? Sorry but this seems like >>> an awfully terse commit message. >> >> To ensure clocks are disabled and to save power in low power modes used >> on 7211 for instance. > > Thanks for the explanation, that's an important tidbit. I wasn't even > aware that this SPI controller is used on SoCs beyond the Raspberry Pi > ones. Does the BCM7211 use shared interrupts for this controller? > Does it have DMA DREQ attached? For all practical purposes you can consider that 7211 is identical to a 2711, it does use shared interrupts for this controller and there is a DRAM DREQ attached as well. Where they differ are on the display, video, and memory controller MAC. -- Florian