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Fri, 29 May 2020 15:28:24 -0700 Received: from [172.19.2.244] (helo=localhost) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jenUF-00036d-UV; Fri, 29 May 2020 15:28:23 -0700 Date: Fri, 29 May 2020 15:28:23 -0700 From: Hyun Kwon To: Laurent Pinchart Cc: Hyun Kwon , Venkateshwar Rao Gannavarapu , "dri-devel@lists.freedesktop.org" , "airlied@linux.ie" , "daniel@ffwll.ch" , "linux-kernel@vger.kernel.org" , Sandip Kothari Subject: Re: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem Message-ID: <20200529222823.GA32429@smtp.xilinx.com> References: <1587417656-48078-1-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> <1587417656-48078-3-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> <20200504184348.GA3095@smtp.xilinx.com> <20200524030813.GF6026@pendragon.ideasonboard.com> <20200527175435.GA26381@smtp.xilinx.com> <20200527224524.GH6171@pendragon.ideasonboard.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20200527224524.GH6171@pendragon.ideasonboard.com> User-Agent: Mutt/1.5.24 (2015-08-30) X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapsmtpgw01;PTR:unknown-60-83.xilinx.com;CAT:NONE;SFTY:;SFS:(396003)(346002)(376002)(136003)(39860400002)(46966005)(186003)(26005)(8676002)(478600001)(44832011)(426003)(83380400001)(33656002)(2906002)(336012)(4326008)(5660300002)(82740400003)(8936002)(9786002)(6916009)(47076004)(316002)(82310400002)(356005)(70586007)(107886003)(70206006)(1076003)(81166007)(54906003);DIR:OUT;SFP:1101; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 98031c52-bd7c-46df-520a-08d8041f9d6c X-MS-TrafficTypeDiagnostic: BN7PR02MB5250: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-Forefront-PRVS: 04180B6720 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lgLsAvbq0Y5grx7DgwoBQ7YFf7AirJXIBnFK1fb+K0a8lhRQg6k0t5drrYgWUMRenxnjst4a067/19VSXQHQX7GxECEL4cLwByq8j6aY9WdOCaYy19eDwiMKQFFWSUelcx/+kbAorEO3DneAOEJDpmYPowTekomcsh1BCRrPk4yFZddrYSWPFkTJKU1lysbyg/kL3EBxwgnJ1ENcMi3oCihv4YN2FsQLqiqk4MOh0yCTfhTHoiCmeQ2ta3tjHTusPMD1xuSj9HK3/GTyxmmRVVvpT1iyIp5guU4SluOlwL0R8k1xQbwTwwKUiZlL6j3YYEshmvCOaE9WyoqjUiDB76tp9UdjOPWTSdFHwiL//IN5cU6xdg4TA9RfqsVE1n5b+6PoZ72p4a1nlk4sAudVOQ== X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2020 22:28:30.4374 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98031c52-bd7c-46df-520a-08d8041f9d6c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR02MB5250 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Laurent, On Wed, 2020-05-27 at 15:45:24 -0700, Laurent Pinchart wrote: > Hi Hyun, > > On Wed, May 27, 2020 at 10:54:35AM -0700, Hyun Kwon wrote: > > On Sat, 2020-05-23 at 20:08:13 -0700, Laurent Pinchart wrote: > > > On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote: > > >> On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote: > > >>> The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video > > >>> data from AXI-4 stream interface. > > >>> > > >>> It supports upto 4 lanes, optional register interface for the DPHY, > > >> > > >> I don't see the register interface for dphy support. > > > > > > I think the D-PHY should be supported through a PHY driver, as it seems > > > to be shared between different subsystems. > > > > Right, if the logic is shared across subsystems. I can't tell if that's > > the case as the IP comes as a single block. Maybe GVRao can confirm. > > I believe the CSI2-RX subsystem uses the same D-PHY IP core, but a > confirmation would be nice. > > > >>> multiple RGB color formats, command mode and video mode. > > >>> This is a MIPI-DSI host driver and provides DSI bus for panels. > > >>> This driver also helps to communicate with its panel using panel > > >>> framework. > > >>> > > >>> Signed-off-by: Venkateshwar Rao Gannavarapu > > >>> --- > > >>> drivers/gpu/drm/xlnx/Kconfig | 11 + > > >>> drivers/gpu/drm/xlnx/Makefile | 2 + > > >>> drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 ++++++++++++++++++++++++++++++++++++++++ > > > > > > Daniel Vetter has recently expressed his opiion that bridge drivers > > > should go to drivers/gpu/drm/bridge/. It would then be > > > drivers/gpu/drm/bridge/xlnx/. I don't have a strong opinion myself. > > > > > >>> 3 files changed, 768 insertions(+) > > >>> create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c > > >>> > > >>> diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig > > >>> index aa6cd88..73873cf 100644 > > >>> --- a/drivers/gpu/drm/xlnx/Kconfig > > >>> +++ b/drivers/gpu/drm/xlnx/Kconfig > > >>> @@ -11,3 +11,14 @@ config DRM_ZYNQMP_DPSUB > > >>> This is a DRM/KMS driver for ZynqMP DisplayPort controller. Choose > > >>> this option if you have a Xilinx ZynqMP SoC with DisplayPort > > >>> subsystem. > > >>> + > > >>> +config DRM_XLNX_DSI > > >>> + tristate "Xilinx DRM DSI Subsystem Driver" > > >>> + select DRM_MIPI_DSI > > >>> + select DRM_PANEL > > >>> + select DRM_PANEL_SIMPLE > > >>> + help > > >>> + This enables support for Xilinx MIPI-DSI. > > >> > > >> This sentence is not needed with below. Could you please rephrase the whole? > > >> > > >>> + This is a DRM/KMS driver for Xilinx programmable DSI controller. > > >>> + Choose this option if you have a Xilinx MIPI DSI-TX controller > > >>> + subsytem. > > >> > > >> These seem incorrectly indented. > > >> > > >>> diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile > > >>> index 2b844c6..b7ee6ef 100644 > > >>> --- a/drivers/gpu/drm/xlnx/Makefile > > >>> +++ b/drivers/gpu/drm/xlnx/Makefile > > >>> @@ -1,2 +1,4 @@ > > >>> zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o > > >>> obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o > > >>> + > > >>> +obj-$(CONFIG_DRM_XLNX_DSI) += xlnx_dsi.o > > >>> diff --git a/drivers/gpu/drm/xlnx/xlnx_dsi.c b/drivers/gpu/drm/xlnx/xlnx_dsi.c > > >>> new file mode 100644 > > >>> index 0000000..b8cae59 > > >>> --- /dev/null > > >>> +++ b/drivers/gpu/drm/xlnx/xlnx_dsi.c > > >>> @@ -0,0 +1,755 @@ > > >>> +// SPDX-License-Identifier: GPL-2.0 > > >>> +/* > > >>> + * Xilinx FPGA MIPI DSI Tx Controller driver > > >>> + * > > >>> + * Copyright (C) 2017 - 2019 Xilinx, Inc. > > >>> + * > > >>> + * Authors: > > >>> + * - Saurabh Sengar > > >>> + * - Venkateshwar Rao Gannavarapu > > >>> + */ > > >>> + > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> + > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> +#include > > >>> + > > >>> +#include