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Sun, 31 May 2020 09:13:19 +0200 Received: from vleu-orange.cadence.com (10.160.88.83) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Sun, 31 May 2020 09:13:19 +0200 Received: from vleu-orange.cadence.com (localhost.localdomain [127.0.0.1]) by vleu-orange.cadence.com (8.14.4/8.14.4) with ESMTP id 04V7DJcV006692; Sun, 31 May 2020 09:13:19 +0200 Received: (from pthombar@localhost) by vleu-orange.cadence.com (8.14.4/8.14.4/Submit) id 04V7DJ6D006691; Sun, 31 May 2020 09:13:19 +0200 From: Parshuram Thombare To: , CC: , , , , , Parshuram Thombare Subject: [PATCH v8 3/7] i3c: master: add i3c_secondary_master_register Date: Sun, 31 May 2020 09:13:18 +0200 Message-ID: <1590909198-6650-1-git-send-email-pthombar@cadence.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1590909063-6013-1-git-send-email-pthombar@cadence.com> References: <1590909063-6013-1-git-send-email-pthombar@cadence.com> MIME-Version: 1.0 Content-Type: text/plain X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:199.43.4.23;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:rmmaillnx1.cadence.com;PTR:InfoDomainNonexistent;CAT:NONE;SFTY:;SFS:(4636009)(346002)(376002)(39850400004)(136003)(396003)(36092001)(46966005)(70586007)(8676002)(70206006)(42186006)(478600001)(2906002)(186003)(36906005)(316002)(83380400001)(86362001)(54906003)(110136005)(107886003)(426003)(8936002)(47076004)(82740400003)(82310400002)(5660300002)(336012)(2616005)(26005)(4326008)(356005)(81166007)(36756003);DIR:OUT;SFP:1101; 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Signed-off-by: Parshuram Thombare --- drivers/i3c/master.c | 154 ++++++++++++++++++++++++++++++++++++- include/linux/i3c/master.h | 3 + 2 files changed, 156 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 574c3603db38..62f39997a6db 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -1768,6 +1768,90 @@ static int i3c_primary_master_bus_init(struct i3c_master_controller *master) return ret; } +/** + * i3c_secondary_master_bus_init() - initialize an I3C bus for secondary + * master + * @master: secondary master initializing the bus + * + * This function does + * + * 1. Attach I2C devs to the master + * + * 2. Call &i3c_master_controller_ops->bus_init() method to initialize + * the master controller. That's usually where the bus mode is selected + * (pure bus or mixed fast/slow bus) + * + * Once this is done, I2C devices should be usable. + * + * Return: a 0 in case of success, an negative error code otherwise. + */ +static int i3c_secondary_master_bus_init(struct i3c_master_controller *master) +{ + enum i3c_addr_slot_status status; + struct i2c_dev_boardinfo *i2cboardinfo; + struct i2c_dev_desc *i2cdev; + int ret; + + /* + * First attach all devices with static definitions provided by the + * FW. + */ + list_for_each_entry(i2cboardinfo, &master->boardinfo.i2c, node) { + status = i3c_bus_get_addr_slot_status(&master->bus, + i2cboardinfo->base.addr); + if (status != I3C_ADDR_SLOT_FREE) { + ret = -EBUSY; + goto err_detach_devs; + } + + i3c_bus_set_addr_slot_status(&master->bus, + i2cboardinfo->base.addr, + I3C_ADDR_SLOT_I2C_DEV); + + i2cdev = i3c_master_alloc_i2c_dev(master, i2cboardinfo); + if (IS_ERR(i2cdev)) { + ret = PTR_ERR(i2cdev); + goto err_detach_devs; + } + + ret = i3c_master_attach_i2c_dev(master, i2cdev); + if (ret) { + i3c_master_free_i2c_dev(i2cdev); + goto err_detach_devs; + } + } + + /* + * Now execute the controller specific ->bus_init() routine, which + * might configure its internal logic to match the bus limitations. + */ + ret = master->ops->bus_init(master); + if (ret) + goto err_detach_devs; + + /* + * The master device should have been instantiated in ->bus_init(), + * complain if this was not the case. + */ + if (!master->this) { + dev_err(&master->dev, + "master_set_info() was not called in ->bus_init()\n"); + ret = -EINVAL; + goto err_bus_cleanup; + } + + return 0; + +err_bus_cleanup: + if (master->ops->bus_cleanup) + master->ops->bus_cleanup(master); + +err_detach_devs: + i3c_master_detach_free_devs(master); + + return ret; +} + static void i3c_master_bus_cleanup(struct i3c_master_controller *master) { if (master->ops->bus_cleanup) @@ -2457,7 +2541,10 @@ static int i3c_master_init(struct i3c_master_controller *master, goto err_put_dev; } - ret = i3c_primary_master_bus_init(master); + if (secondary) + ret = i3c_secondary_master_bus_init(master); + else + ret = i3c_primary_master_bus_init(master); if (ret) goto err_put_dev; @@ -2532,6 +2619,71 @@ int i3c_primary_master_register(struct i3c_master_controller *master, } EXPORT_SYMBOL_GPL(i3c_primary_master_register); +/** + * i3c_secondary_master_register() - register an I3C secondary master + * @master: master used to send frames on the bus + * @parent: the parent device (the one that provides this I3C master + * controller) + * @ops: the master controller operations + * + * This function does minimal required initialization for secondary + * master, rest functionality like creating and registering I2C + * and I3C devices is done in defslvs processing. + * + * i3c_secondary_master_register() does following things - + * - creates and initializes the I3C bus + * - populates the bus with static I2C devs if @parent->of_node is not + * NULL + * initialization + * - allocate memory for defslvs_data.devs, which is used to receive + * defslvs list + * - create I3C device representing this master + * - registers the I2C adapter and all I2C devices + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int i3c_secondary_master_register(struct i3c_master_controller *master, + struct device *parent, + const struct i3c_master_controller_ops *ops) +{ + int ret; + + ret = i3c_master_init(master, parent, ops, true); + if (ret) + return ret; + + ret = device_add(&master->dev); + if (ret) + goto err_cleanup_bus; + + /* + * Expose our I3C bus as an I2C adapter so that I2C devices are exposed + * through the I2C subsystem. + */ + ret = i3c_master_i2c_adapter_init(master); + if (ret) + goto err_del_dev; + + /* + * We're done initializing the bus and the controller, we can now + * register I3C devices from defslvs list. + */ + master->init_done = true; + + return 0; + +err_del_dev: + device_del(&master->dev); + +err_cleanup_bus: + i3c_master_bus_cleanup(master); + + put_device(&master->dev); + + return ret; +} +EXPORT_SYMBOL_GPL(i3c_secondary_master_register); + /** * i3c_master_unregister() - unregister an I3C master * @master: master used to send frames on the bus diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h index a19d0ad4de8a..c3d05f66fceb 100644 --- a/include/linux/i3c/master.h +++ b/include/linux/i3c/master.h @@ -534,6 +534,9 @@ int i3c_master_set_info(struct i3c_master_controller *master, int i3c_primary_master_register(struct i3c_master_controller *master, struct device *parent, const struct i3c_master_controller_ops *ops); +int i3c_secondary_master_register(struct i3c_master_controller *master, + struct device *parent, + const struct i3c_master_controller_ops *ops); int i3c_master_unregister(struct i3c_master_controller *master); /** -- 2.17.1