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[83.6.167.130]) by smtp.googlemail.com with ESMTPSA id b81sm8922326wmc.5.2020.05.31.10.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 May 2020 10:28:26 -0700 (PDT) From: Konrad Dybcio Cc: Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/14] arm64: dts: msm8992: Add PMU node Date: Sun, 31 May 2020 19:28:00 +0200 Message-Id: <20200531172804.256335-11-konradybcio@gmail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200531172804.256335-1-konradybcio@gmail.com> References: <20200531172804.256335-1-konradybcio@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit To: unlisted-recipients:; (no To-header on input) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the PMU so we can get proper perf event support on this SoC. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index ef95f5ee83db..b86fcfb6f463 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -381,6 +381,11 @@ smem_region: smem@6a00000 { }; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + smd_rpm: smd { compatible = "qcom,smd"; rpm { -- 2.26.2