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From:   Konrad Dybcio <konradybcio@gmail.com>
Cc:     Konrad Dybcio <konradybcio@gmail.com>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 2/4] Add compatible strings and the include files for the msm8992 GCC.
Date:   Sun, 31 May 2020 19:46:08 +0200
Message-Id: <20200531174612.260113-3-konradybcio@gmail.com>
In-Reply-To: <20200531174612.260113-1-konradybcio@gmail.com>
References: <20200531174612.260113-1-konradybcio@gmail.com>
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This commit adds the include files and documents compatible
strings for the msm8992 GCC driver

Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
---
 .../devicetree/bindings/clock/qcom,gcc.yaml   |   2 +
 include/dt-bindings/clock/qcom,gcc-msm8992.h  | 144 ++++++++++++++++++
 include/dt-bindings/reset/qcom,gcc-msm8992.h  |   8 +
 3 files changed, 154 insertions(+)
 create mode 100644 include/dt-bindings/clock/qcom,gcc-msm8992.h
 create mode 100644 include/dt-bindings/reset/qcom,gcc-msm8992.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
index e533bb0cfd2b..66e51f2c0c27 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
@@ -26,6 +26,7 @@ description: |
   - dt-bindings/reset/qcom,gcc-msm8660.h
   - dt-bindings/clock/qcom,gcc-msm8974.h
   - dt-bindings/reset/qcom,gcc-msm8974.h
+  - dt-bindings/reset/qcom,gcc-msm8992.h
   - dt-bindings/clock/qcom,gcc-msm8994.h
   - dt-bindings/clock/qcom,gcc-mdm9615.h
   - dt-bindings/reset/qcom,gcc-mdm9615.h
@@ -45,6 +46,7 @@ properties:
       - qcom,gcc-msm8974
       - qcom,gcc-msm8974pro
       - qcom,gcc-msm8974pro-ac
+      - qcom,gcc-msm8992
       - qcom,gcc-msm8994
       - qcom,gcc-mdm9615
       - qcom,gcc-sdm630
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8992.h b/include/dt-bindings/clock/qcom,gcc-msm8992.h
new file mode 100644
index 000000000000..8591a881005d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8992.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ */
+
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8992_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8992_H
+
+#define GPLL0_EARLY                     0
+#define GPLL0                           1
+#define GPLL4_EARLY                     2
+#define GPLL4                           3
+#define USB30_MASTER_CLK_SRC            4
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC     5
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC     6
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC     7
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC     8
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC     9
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC     10
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC     11
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC     12
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC     13
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC     14
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC     15
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC     16
+#define BLSP1_UART1_APPS_CLK_SRC        17
+#define BLSP1_UART2_APPS_CLK_SRC        18
+#define BLSP1_UART3_APPS_CLK_SRC        19
+#define BLSP1_UART4_APPS_CLK_SRC        20
+#define BLSP1_UART5_APPS_CLK_SRC        21
+#define BLSP1_UART6_APPS_CLK_SRC        22
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC     23
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC     24
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC     25
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC     26
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC     27
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC     28
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC     29
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC     30
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC     31
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC     32
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC     33
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC     34
+#define BLSP2_UART1_APPS_CLK_SRC        35
+#define BLSP2_UART2_APPS_CLK_SRC        36
+#define BLSP2_UART3_APPS_CLK_SRC        37
+#define BLSP2_UART4_APPS_CLK_SRC        38
+#define BLSP2_UART5_APPS_CLK_SRC        39
+#define BLSP2_UART6_APPS_CLK_SRC        40
+#define GP1_CLK_SRC                     41
+#define GP2_CLK_SRC                     42
+#define GP3_CLK_SRC                     43
+#define PCIE_0_AUX_CLK_SRC              44
+#define PCIE_0_PIPE_CLK_SRC             45
+#define PDM2_CLK_SRC                    46
+#define SDCC1_APPS_CLK_SRC              47
+#define SDCC2_APPS_CLK_SRC              48
+#define SDCC3_APPS_CLK_SRC              49
+#define SDCC4_APPS_CLK_SRC              50
+#define TSIF_REF_CLK_SRC                51
+#define USB30_MOCK_UTMI_CLK_SRC         52
+#define USB3_PHY_AUX_CLK_SRC            53
+#define USB_HS_SYSTEM_CLK_SRC           54
+#define GCC_BLSP1_AHB_CLK               55
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK     56
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK     57
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK     58
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK     59
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK     60
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK     61
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK     62
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK     63
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK     64
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK     65
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK     66
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK     67
+#define GCC_BLSP1_UART1_APPS_CLK        69
+#define GCC_BLSP1_UART2_APPS_CLK        70
+#define GCC_BLSP1_UART3_APPS_CLK        71
+#define GCC_BLSP1_UART4_APPS_CLK        72
+#define GCC_BLSP1_UART5_APPS_CLK        73
+#define GCC_BLSP1_UART6_APPS_CLK        74
+#define GCC_BLSP2_AHB_CLK               75
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK     76
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK     77
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK     78
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK     79
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK     80
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK     81
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK     82
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK     83
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK     84
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK     85
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK     86
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK     87
+#define GCC_BLSP2_UART1_APPS_CLK        88
+#define GCC_BLSP2_UART2_APPS_CLK        89
+#define GCC_BLSP2_UART3_APPS_CLK        90
+#define GCC_BLSP2_UART4_APPS_CLK        91
+#define GCC_BLSP2_UART5_APPS_CLK        92
+#define GCC_BLSP2_UART6_APPS_CLK        93
+#define GCC_BOOT_ROM_AHB_CLK            94
+#define GCC_GP1_CLK                     95
+#define GCC_GP2_CLK                     96
+#define GCC_GP3_CLK                     97
+#define GCC_MSS_CFG_AHB_CLK             98
+#define GCC_MSS_Q6_BIMC_AXI_CLK         99
+#define GCC_PCIE_0_AUX_CLK              100
+#define GCC_PCIE_0_CFG_AHB_CLK          101
+#define GCC_PCIE_0_MSTR_AXI_CLK         102
+#define GCC_PCIE_0_PIPE_CLK             103
+#define GCC_PCIE_0_SLV_AXI_CLK          104
+#define GCC_PDM2_CLK                    105
+#define GCC_PDM_AHB_CLK                 106
+#define GCC_PRNG_AHB_CLK                107
+#define GCC_SDCC1_AHB_CLK               108
+#define GCC_SDCC1_APPS_CLK              109
+#define GCC_SDCC2_AHB_CLK               110
+#define GCC_SDCC2_APPS_CLK              111
+#define GCC_SDCC3_AHB_CLK               112
+#define GCC_SDCC3_APPS_CLK              113
+#define GCC_SDCC4_AHB_CLK               114
+#define GCC_SDCC4_APPS_CLK              115
+#define GCC_SYS_NOC_USB3_AXI_CLK        116
+#define GCC_TSIF_AHB_CLK                117
+#define GCC_TSIF_REF_CLK                118
+#define GCC_USB2_HS_PHY_SLEEP_CLK       119
+#define GCC_USB30_MASTER_CLK            120
+#define GCC_USB30_MOCK_UTMI_CLK         121
+#define	GCC_USB30_SLEEP_CLK             122
+#define GCC_USB3_PHY_AUX_CLK            123
+#define GCC_USB3_PHY_PIPE_CLK           124
+#define GCC_USB_HS_AHB_CLK              125
+#define GCC_USB_HS_SYSTEM_CLK           126
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK     127
+
+
+/* Indexes for GDSCs */
+#define PCIE_GDSC                       0
+#define PCIE_0_GDSC                     1
+#define USB30_GDSC                      2
+
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8992.h b/include/dt-bindings/reset/qcom,gcc-msm8992.h
new file mode 100644
index 000000000000..558dfeffdeef
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-msm8992.h
@@ -0,0 +1,8 @@
+#ifndef _DT_BINDINGS_RESET_MSM_GCC_8992_H
+#define _DT_BINDINGS_RESET_MSM_GCC_8992_H
+
+#define PCIE_PHY_0_RESET 0
+#define QUSB2_PHY_RESET 1
+#define USB3_PHY_RESET 2
+
+#endif
-- 
2.26.2