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Mon, 1 Jun 2020 08:30:44 +0000 From: peng.fan@nxp.com To: shawnguo@kernel.org, fabio.estevam@nxp.com, kernel@pengutronix.de, aisheng.dong@nxp.com, robh+dt@kernel.org, sboyd@kernel.org, linux@rempel-privat.de, jaswinder.singh@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com, leonard.crestez@nxp.com, daniel.baluta@nxp.com, l.stach@pengutronix.de, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Peng Fan Subject: [PATCH V3 3/3] clk: imx8mp: add mu root clk Date: Mon, 1 Jun 2020 16:20:02 +0800 Message-Id: <1590999602-29482-4-git-send-email-peng.fan@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590999602-29482-1-git-send-email-peng.fan@nxp.com> References: <1590999602-29482-1-git-send-email-peng.fan@nxp.com> Content-Type: text/plain X-ClientProxiedBy: SG2PR02CA0044.apcprd02.prod.outlook.com (2603:1096:3:18::32) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR02CA0044.apcprd02.prod.outlook.com (2603:1096:3:18::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3021.27 via Frontend Transport; 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Reviewed-by: Dong Aisheng Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8mp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index b4d9db9d5bf1..ca747712400f 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -680,6 +680,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", ccm_base + 0x4180, 0); hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", ccm_base + 0x4190, 0); hws[IMX8MP_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", ccm_base + 0x41a0, 0); + hws[IMX8MP_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", ccm_base + 0x4210, 0); hws[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", ccm_base + 0x4220, 0); hws[IMX8MP_CLK_PCIE_ROOT] = imx_clk_hw_gate4("pcie_root_clk", "pcie_aux", ccm_base + 0x4250, 0); hws[IMX8MP_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", ccm_base + 0x4280, 0); -- 2.16.4