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[23.128.96.18]) by mx.google.com with ESMTP id c24si238855edv.129.2020.06.01.12.50.32; Mon, 01 Jun 2020 12:50:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20161025 header.b=bF2QN7Z3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728360AbgFATri (ORCPT + 99 others); Mon, 1 Jun 2020 15:47:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727099AbgFATri (ORCPT ); Mon, 1 Jun 2020 15:47:38 -0400 Received: from mail-pj1-x1043.google.com (mail-pj1-x1043.google.com [IPv6:2607:f8b0:4864:20::1043]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0FF9C061A0E for ; Mon, 1 Jun 2020 12:47:37 -0700 (PDT) Received: by mail-pj1-x1043.google.com with SMTP id nm22so268787pjb.4 for ; Mon, 01 Jun 2020 12:47:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=LyvA62biKTQGNyyqx4DnGpsV+JYlCmkfnivzJZ0J7rU=; b=bF2QN7Z3Im/VQTjcR3/xlJQHRUN0MP+Yx+hwfS/ip45iFEUwHQfFFZR1V/lYCQr6ef 4DaTEh7g3277Q5SOHYmtLT9E6TKShfmt+nhNVcN++LbNmnuqZFcpfPbbqcehv0VAMEgR 8O+d2L/mkPDCiGDSqkYs1SWvSIk40mFNC1HsdKKKOoC3E4xWKshB341mfFeX3Eyk8fhe +dq1WcRJ6CwDoQ06pOkv4WNhjrIGAjyKb3gxd5Bx8JzYAr6VNBK4yucqRHopI7gEpAiS uBkbvSo6pR1aN5w8ptcn3NdDK9Zgsxv7+OAMij5ca6XhfH6T+h+2nBvAvxXsS/0Yk83T KaDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=LyvA62biKTQGNyyqx4DnGpsV+JYlCmkfnivzJZ0J7rU=; b=WwkmY6dMUp1uoMy4QJBJvJTakdouw79qPvDJ7sQCSCqTpcx/O5lPQlqCuKgKUbGyWn z1z+0b5wS3+RRDSB36flwEu1CXVIdDZF5RggXbwJ64+q5CZjClMcBUy1PshM/fi+X/7j VPzF9FanPPw7rrqnN047mnD6U3kw8uLNyHLOum7B2NrI+eCw+rgChbwZXe5XSzQ3HOhn urev0db94aYrv08aDCUDAGL6uP/TFicqOnX8nIC01FnbiXHxE1xqQAORdReqXD/0uroZ LQ68aobcJ+/ZJgJPRZlXUMHrGBDX6H4mTipMm8J5To4D+Dit7d9d2rhcCqfAf1Y8FU+k kqaw== X-Gm-Message-State: AOAM533ltrfTFwulZD/IYk/IZNNQYwAsMaT/esZDAKKdA1QyN0r3sr3L xdFc91ADN0Y1IjFGDwWBQVRiONAzsNAKR1+QUlAOeg== X-Received: by 2002:a17:90b:4c47:: with SMTP id np7mr1109786pjb.101.1591040856878; Mon, 01 Jun 2020 12:47:36 -0700 (PDT) MIME-Version: 1.0 References: <20200530221127.459704-1-brgerst@gmail.com> <20200530221127.459704-7-brgerst@gmail.com> In-Reply-To: <20200530221127.459704-7-brgerst@gmail.com> From: Nick Desaulniers Date: Mon, 1 Jun 2020 12:47:25 -0700 Message-ID: Subject: Re: [PATCH v2 06/10] x86/percpu: Clean up percpu_add_return_op() To: Brian Gerst Cc: LKML , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H . Peter Anvin" , Andy Lutomirski , Peter Zijlstra Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, May 30, 2020 at 3:11 PM Brian Gerst wrote: > > The core percpu macros already have a switch on the data size, so the switch > in the x86 code is redundant and produces more dead code. > > Also use appropriate types for the width of the instructions. This avoids > errors when compiling with Clang. > > Signed-off-by: Brian Gerst I think it would have been ok to carry forward my reviewed by tag here from v1, hidden at the bottom of https://lore.kernel.org/lkml/CAKwvOdn7yC1GVA+6gtNewBSq2BK09y9iNWhv1dPFF5i4kT1+6A@mail.gmail.com/ even though you split removing 'e' into it's own patch. Reviewed-by: Nick Desaulniers > --- > arch/x86/include/asm/percpu.h | 51 +++++++++++------------------------ > 1 file changed, 16 insertions(+), 35 deletions(-) > > diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h > index 9bb5440d98d3..0776a11e7e11 100644 > --- a/arch/x86/include/asm/percpu.h > +++ b/arch/x86/include/asm/percpu.h > @@ -199,34 +199,15 @@ do { \ > /* > * Add return operation > */ > -#define percpu_add_return_op(qual, var, val) \ > +#define percpu_add_return_op(size, qual, _var, _val) \ > ({ \ > - typeof(var) paro_ret__ = val; \ > - switch (sizeof(var)) { \ > - case 1: \ > - asm qual ("xaddb %0, "__percpu_arg(1) \ > - : "+q" (paro_ret__), "+m" (var) \ > - : : "memory"); \ > - break; \ > - case 2: \ > - asm qual ("xaddw %0, "__percpu_arg(1) \ > - : "+r" (paro_ret__), "+m" (var) \ > - : : "memory"); \ > - break; \ > - case 4: \ > - asm qual ("xaddl %0, "__percpu_arg(1) \ > - : "+r" (paro_ret__), "+m" (var) \ > - : : "memory"); \ > - break; \ > - case 8: \ > - asm qual ("xaddq %0, "__percpu_arg(1) \ > - : "+r" (paro_ret__), "+m" (var) \ > - : : "memory"); \ > - break; \ > - default: __bad_percpu_size(); \ > - } \ > - paro_ret__ += val; \ > - paro_ret__; \ > + __pcpu_type_##size paro_tmp__ = __pcpu_cast_##size(_val); \ > + asm qual (__pcpu_op2_##size("xadd", "%[tmp]", \ > + __percpu_arg([var])) \ > + : [tmp] __pcpu_reg_##size("+", paro_tmp__), \ > + [var] "+m" (_var) \ > + : : "memory"); \ > + (typeof(_var))(unsigned long) (paro_tmp__ + _val); \ > }) > > /* > @@ -377,16 +358,16 @@ do { \ > #define this_cpu_xchg_2(pcp, nval) percpu_xchg_op(volatile, pcp, nval) > #define this_cpu_xchg_4(pcp, nval) percpu_xchg_op(volatile, pcp, nval) > > -#define raw_cpu_add_return_1(pcp, val) percpu_add_return_op(, pcp, val) > -#define raw_cpu_add_return_2(pcp, val) percpu_add_return_op(, pcp, val) > -#define raw_cpu_add_return_4(pcp, val) percpu_add_return_op(, pcp, val) > +#define raw_cpu_add_return_1(pcp, val) percpu_add_return_op(1, , pcp, val) > +#define raw_cpu_add_return_2(pcp, val) percpu_add_return_op(2, , pcp, val) > +#define raw_cpu_add_return_4(pcp, val) percpu_add_return_op(4, , pcp, val) > #define raw_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(, pcp, oval, nval) > #define raw_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(, pcp, oval, nval) > #define raw_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(, pcp, oval, nval) > > -#define this_cpu_add_return_1(pcp, val) percpu_add_return_op(volatile, pcp, val) > -#define this_cpu_add_return_2(pcp, val) percpu_add_return_op(volatile, pcp, val) > -#define this_cpu_add_return_4(pcp, val) percpu_add_return_op(volatile, pcp, val) > +#define this_cpu_add_return_1(pcp, val) percpu_add_return_op(1, volatile, pcp, val) > +#define this_cpu_add_return_2(pcp, val) percpu_add_return_op(2, volatile, pcp, val) > +#define this_cpu_add_return_4(pcp, val) percpu_add_return_op(4, volatile, pcp, val) > #define this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(volatile, pcp, oval, nval) > #define this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(volatile, pcp, oval, nval) > #define this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(volatile, pcp, oval, nval) > @@ -418,7 +399,7 @@ do { \ > #define raw_cpu_add_8(pcp, val) percpu_add_op(8, , (pcp), val) > #define raw_cpu_and_8(pcp, val) percpu_to_op(8, , "and", (pcp), val) > #define raw_cpu_or_8(pcp, val) percpu_to_op(8, , "or", (pcp), val) > -#define raw_cpu_add_return_8(pcp, val) percpu_add_return_op(, pcp, val) > +#define raw_cpu_add_return_8(pcp, val) percpu_add_return_op(8, , pcp, val) > #define raw_cpu_xchg_8(pcp, nval) raw_percpu_xchg_op(pcp, nval) > #define raw_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(, pcp, oval, nval) > > @@ -427,7 +408,7 @@ do { \ > #define this_cpu_add_8(pcp, val) percpu_add_op(8, volatile, (pcp), val) > #define this_cpu_and_8(pcp, val) percpu_to_op(8, volatile, "and", (pcp), val) > #define this_cpu_or_8(pcp, val) percpu_to_op(8, volatile, "or", (pcp), val) > -#define this_cpu_add_return_8(pcp, val) percpu_add_return_op(volatile, pcp, val) > +#define this_cpu_add_return_8(pcp, val) percpu_add_return_op(8, volatile, pcp, val) > #define this_cpu_xchg_8(pcp, nval) percpu_xchg_op(volatile, pcp, nval) > #define this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(volatile, pcp, oval, nval) > > -- > 2.25.4 > -- Thanks, ~Nick Desaulniers