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From:   <ansuelsmth@gmail.com>
To:     "'Stanimir Varbanov'" <svarbanov@mm-sol.com>,
        "'Bjorn Andersson'" <bjorn.andersson@linaro.org>
Cc:     "'Sham Muthayyan'" <smuthayy@codeaurora.org>,
        "'Andy Gross'" <agross@kernel.org>,
        "'Bjorn Helgaas'" <bhelgaas@google.com>,
        "'Rob Herring'" <robh+dt@kernel.org>,
        "'Mark Rutland'" <mark.rutland@arm.com>,
        "'Lorenzo Pieralisi'" <lorenzo.pieralisi@arm.com>,
        "'Andrew Murray'" <amurray@thegoodpenguin.co.uk>,
        "'Philipp Zabel'" <p.zabel@pengutronix.de>,
        <linux-arm-msm@vger.kernel.org>, <linux-pci@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
References: <20200514200712.12232-1-ansuelsmth@gmail.com> <20200514200712.12232-9-ansuelsmth@gmail.com> <e672c516-29a4-e7d2-ee8b-3bce73bdf4e2@mm-sol.com>
In-Reply-To: <e672c516-29a4-e7d2-ee8b-3bce73bdf4e2@mm-sol.com>
Subject: R: [PATCH v4 08/10] PCI: qcom: Add ipq8064 rev2 variant and set tx term offset
Date:   Tue, 2 Jun 2020 11:31:27 +0200
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> -----Messaggio originale-----
> Da: Stanimir Varbanov <svarbanov@mm-sol.com>
> Inviato: marted=C3=AC 2 giugno 2020 09:54
> A: Ansuel Smith <ansuelsmth@gmail.com>; Bjorn Andersson
> <bjorn.andersson@linaro.org>
> Cc: Sham Muthayyan <smuthayy@codeaurora.org>; Andy Gross
> <agross@kernel.org>; Bjorn Helgaas <bhelgaas@google.com>; Rob Herring
> <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; Lorenzo
> Pieralisi <lorenzo.pieralisi@arm.com>; Andrew Murray
> <amurray@thegoodpenguin.co.uk>; Philipp Zabel
> <p.zabel@pengutronix.de>; linux-arm-msm@vger.kernel.org; linux-
> pci@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Oggetto: Re: [PATCH v4 08/10] PCI: qcom: Add ipq8064 rev2 variant and
> set tx term offset
>=20
> Hi,
>=20
> On 5/14/20 11:07 PM, Ansuel Smith wrote:
> > Add tx term offset support to pcie qcom driver need in some revision =
of
> > the ipq806x SoC. Ipq8064 have tx term offset set to 7. Ipq8064-v2
> revision
> > and ipq8065 have the tx term offset set to 0.
> >
> > Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > ---
> >  drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++++++++++--
> >  1 file changed, 16 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
> b/drivers/pci/controller/dwc/pcie-qcom.c
> > index f5398b0d270c..ab6f1bdd24c3 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -45,6 +45,9 @@
> >  #define PCIE_CAP_CPL_TIMEOUT_DISABLE		0x10
> >
> >  #define PCIE20_PARF_PHY_CTRL			0x40
> > +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK	GENMASK(20,
> 16)
>=20
> I see you changed the mask, did you found the issue in previous v3 =
mask
> and shift?
>=20

I checked the original code and the old GENMASK declaration was wrong as =
you
suggested.

> > +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)		((x) << 16)
> > +
> >  #define PCIE20_PARF_PHY_REFCLK			0x4C
> >  #define PHY_REFCLK_SSP_EN			BIT(16)
> >  #define PHY_REFCLK_USE_PAD			BIT(12)
> > @@ -363,7 +366,8 @@ static int qcom_pcie_init_2_1_0(struct
> qcom_pcie *pcie)
> >  	val &=3D ~BIT(0);
> >  	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
> >
> > -	if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
> > +	if (of_device_is_compatible(node, "qcom,pcie-ipq8064") |
>=20
> this should be logical OR
>=20

Will change in v5 since I will have to split this

> > +	    of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
> >  		writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
> >  			       PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
> >  			       PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
> > @@ -374,9 +378,18 @@ static int qcom_pcie_init_2_1_0(struct
> qcom_pcie *pcie)
> >  		writel(PHY_RX0_EQ(4), pcie->parf +
> PCIE20_PARF_CONFIG_BITS);
> >  	}
> >
> > +	if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
> > +		/* set TX termination offset */
> > +		val =3D readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
> > +		val &=3D ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
> > +		val |=3D PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
> > +		writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
> > +	}
> > +
> >  	/* enable external reference clock */
> >  	val =3D readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
> > -	val |=3D BIT(16);
> > +	val &=3D ~PHY_REFCLK_USE_PAD;
> > +	val |=3D PHY_REFCLK_SSP_EN;
> >  	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
> >
> >  	/* wait for clock acquisition */
> > @@ -1452,6 +1465,7 @@ static int qcom_pcie_probe(struct
> platform_device *pdev)
> >  static const struct of_device_id qcom_pcie_match[] =3D {
> >  	{ .compatible =3D "qcom,pcie-apq8084", .data =3D &ops_1_0_0 },
> >  	{ .compatible =3D "qcom,pcie-ipq8064", .data =3D &ops_2_1_0 },
> > +	{ .compatible =3D "qcom,pcie-ipq8064-v2", .data =3D &ops_2_1_0 },
> >  	{ .compatible =3D "qcom,pcie-apq8064", .data =3D &ops_2_1_0 },
> >  	{ .compatible =3D "qcom,pcie-msm8996", .data =3D &ops_2_3_2 },
> >  	{ .compatible =3D "qcom,pcie-ipq8074", .data =3D &ops_2_3_3 },
> >
>=20
> --
> regards,
> Stan