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From:   Andy Shevchenko <andy.shevchenko@gmail.com>
Date:   Tue, 2 Jun 2020 12:59:48 +0300
Message-ID: <CAHp75VdmaGchzGCQ1ch4-9nj=5EKFAndUCKRZKhhiSRrbTwnnA@mail.gmail.com>
Subject: Re: [PATCH 07/15] drm/amdgpu: use PCI_IRQ_MSI_TYPES where appropriate
To:     "Stankiewicz, Piotr" <piotr.stankiewicz@intel.com>
Cc:     Alex Deucher <alexander.deucher@amd.com>,
        =?UTF-8?Q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>,
        David Zhou <David1.Zhou@amd.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        "amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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On Tue, Jun 2, 2020 at 12:58 PM Stankiewicz, Piotr
<piotr.stankiewicz@intel.com> wrote:
> > -----Original Message-----
> > From: Andy Shevchenko <andy.shevchenko@gmail.com>
> > Sent: Tuesday, June 2, 2020 11:49 AM
> > To: Stankiewicz, Piotr <piotr.stankiewicz@intel.com>
> > Cc: Alex Deucher <alexander.deucher@amd.com>; Christian K=C3=B6nig
> > <christian.koenig@amd.com>; David Zhou <David1.Zhou@amd.com>; David
> > Airlie <airlied@linux.ie>; Daniel Vetter <daniel@ffwll.ch>; amd-
> > gfx@lists.freedesktop.org; dri-devel <dri-devel@lists.freedesktop.org>;=
 Linux
> > Kernel Mailing List <linux-kernel@vger.kernel.org>
> > Subject: Re: [PATCH 07/15] drm/amdgpu: use PCI_IRQ_MSI_TYPES where
> > appropriate
> > On Tue, Jun 2, 2020 at 12:24 PM Piotr Stankiewicz
> > <piotr.stankiewicz@intel.com> wrote:

...

> > >                 int nvec =3D pci_msix_vec_count(adev->pdev);
> > >                 unsigned int flags;
> > >
> > > -               if (nvec <=3D 0) {
> > > +               if (nvec > 0)
> > > +                       flags =3D PCI_IRQ_MSI_TYPES;
> > > +               else
> > >                         flags =3D PCI_IRQ_MSI;
> > > -               } else {
> > > -                       flags =3D PCI_IRQ_MSI | PCI_IRQ_MSIX;
> > > -               }
> > > +
> > >                 /* we only need one vector */
> > >                 nvec =3D pci_alloc_irq_vectors(adev->pdev, 1, 1, flag=
s);
> >
> > I'm not sure if you have seen my last comment internally about this pat=
ch.
> >
> > I don't understand why we need these pci_msix_vec_count() followed by
> > conditional at all.
> > Perhaps we may simple drop all these and supply flag directly?
> >
> > But OTOH, I don't know the initial motivation, so, the above patch is
> > non-intrusive and keeps original logic.
> >
>
> Sorry, I must have misunderstood or missed that comment. I am happy
> to do a V2 if dropping the conditional is preferable.

Let's wait for AMD people to confirm either.

--=20
With Best Regards,
Andy Shevchenko