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From:   Andy Shevchenko <andy.shevchenko@gmail.com>
Date:   Tue, 2 Jun 2020 17:00:20 +0300
Message-ID: <CAHp75Vfe5dQkOiFoAZx5b-NS1afiD-YC_w+5LcX8P1Hm0ASenA@mail.gmail.com>
Subject: Re: [PATCH 07/15] drm/amdgpu: use PCI_IRQ_MSI_TYPES where appropriate
To:     "Ruhl, Michael J" <michael.j.ruhl@intel.com>
Cc:     "Stankiewicz, Piotr" <piotr.stankiewicz@intel.com>,
        Alex Deucher <alexander.deucher@amd.com>,
        =?UTF-8?Q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>,
        David Zhou <David1.Zhou@amd.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>,
        "amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
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On Tue, Jun 2, 2020 at 4:38 PM Ruhl, Michael J <michael.j.ruhl@intel.com> w=
rote:
> >-----Original Message-----
> >From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of
> >Piotr Stankiewicz
> >Sent: Tuesday, June 2, 2020 5:21 AM
> >To: Alex Deucher <alexander.deucher@amd.com>; Christian K=C3=B6nig
> ><christian.koenig@amd.com>; David Zhou <David1.Zhou@amd.com>; David
> >Airlie <airlied@linux.ie>; Daniel Vetter <daniel@ffwll.ch>
> >Cc: Stankiewicz, Piotr <piotr.stankiewicz@intel.com>; dri-
> >devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; linux-
> >kernel@vger.kernel.org
> >Subject: [PATCH 07/15] drm/amdgpu: use PCI_IRQ_MSI_TYPES where
> >appropriate

...

> >               int nvec =3D pci_msix_vec_count(adev->pdev);
> >               unsigned int flags;
> >
> >-              if (nvec <=3D 0) {
> >+              if (nvec > 0)
> >+                      flags =3D PCI_IRQ_MSI_TYPES;
> >+              else
> >                       flags =3D PCI_IRQ_MSI;
> >-              } else {
> >-                      flags =3D PCI_IRQ_MSI | PCI_IRQ_MSIX;
> >-              }
>
> Minor nit:
>
> Is it really necessary to set do this check?  Can flags just
> be set?
>
> I.e.:
>         flags =3D PCI_IRQ_MSI_TYPES;
>
> pci_alloc_irq_vector() tries stuff in order.  If MSIX is not available,
> it will try MSI.

That's also what I proposed earlier. But I suggested as well to wait
for AMD people to confirm that neither pci_msix_vec_count() nor flags
is needed and we can directly supply MSI_TYPES to the below call.

> >               /* we only need one vector */
> >               nvec =3D pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);

--=20
With Best Regards,
Andy Shevchenko