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From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Tue, 2 Jun 2020 10:21:12 -0400
Message-ID: <CADnq5_OO=gyo22ZrXp6pDtz2QZ2=LC429u_kkd0ZvX4=M3mBPw@mail.gmail.com>
Subject: Re: [PATCH 07/15] drm/amdgpu: use PCI_IRQ_MSI_TYPES where appropriate
To:     Andy Shevchenko <andy.shevchenko@gmail.com>
Cc:     "Ruhl, Michael J" <michael.j.ruhl@intel.com>,
        David Airlie <airlied@linux.ie>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>,
        "Stankiewicz, Piotr" <piotr.stankiewicz@intel.com>,
        "amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>,
        Alex Deucher <alexander.deucher@amd.com>,
        =?UTF-8?Q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>
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On Tue, Jun 2, 2020 at 10:00 AM Andy Shevchenko
<andy.shevchenko@gmail.com> wrote:
>
> On Tue, Jun 2, 2020 at 4:38 PM Ruhl, Michael J <michael.j.ruhl@intel.com>=
 wrote:
> > >-----Original Message-----
> > >From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of
> > >Piotr Stankiewicz
> > >Sent: Tuesday, June 2, 2020 5:21 AM
> > >To: Alex Deucher <alexander.deucher@amd.com>; Christian K=C3=B6nig
> > ><christian.koenig@amd.com>; David Zhou <David1.Zhou@amd.com>; David
> > >Airlie <airlied@linux.ie>; Daniel Vetter <daniel@ffwll.ch>
> > >Cc: Stankiewicz, Piotr <piotr.stankiewicz@intel.com>; dri-
> > >devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; linux-
> > >kernel@vger.kernel.org
> > >Subject: [PATCH 07/15] drm/amdgpu: use PCI_IRQ_MSI_TYPES where
> > >appropriate
>
> ...
>
> > >               int nvec =3D pci_msix_vec_count(adev->pdev);
> > >               unsigned int flags;
> > >
> > >-              if (nvec <=3D 0) {
> > >+              if (nvec > 0)
> > >+                      flags =3D PCI_IRQ_MSI_TYPES;
> > >+              else
> > >                       flags =3D PCI_IRQ_MSI;
> > >-              } else {
> > >-                      flags =3D PCI_IRQ_MSI | PCI_IRQ_MSIX;
> > >-              }
> >
> > Minor nit:
> >
> > Is it really necessary to set do this check?  Can flags just
> > be set?
> >
> > I.e.:
> >         flags =3D PCI_IRQ_MSI_TYPES;
> >
> > pci_alloc_irq_vector() tries stuff in order.  If MSIX is not available,
> > it will try MSI.
>
> That's also what I proposed earlier. But I suggested as well to wait
> for AMD people to confirm that neither pci_msix_vec_count() nor flags
> is needed and we can directly supply MSI_TYPES to the below call.
>

I think it was leftover from debugging and just to be careful.  We had
some issues when we originally enabled MSI-X on certain boards.  The
fix was to just allocate a single vector (since that is all we use
anyway) and we were using the wrong irq (pdev->irq vs
pci_irq_vector(pdev, 0)).  For reference, the original patch to add
MSI-X:

commit bd660f4f111161f60392dd02424c3a3d2240dc2f
Author: shaoyunl <shaoyun.liu@amd.com>
Date:   Tue Oct 1 15:52:31 2019 -0400

    drm/amdgpu : enable msix for amdgpu driver

    We might used out of the msi resources in some cloud project
    which have a lot gpu devices(including PF and VF), msix can
    provide enough resources from system level view

    Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

And the fix:

commit 8a745c7ff2ddb8511ef760b4d9cb4cf56a15fc8d
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Thu Oct 3 10:34:30 2019 -0500

    drm/amdgpu: improve MSI-X handling (v3)

    Check the number of supported vectors and fall back to MSI if
    we return or error or 0 MSI-X vectors.

    v2: only allocate one vector.  We can't currently use more than
    one anyway.

    v3: install the irq on vector 0.

    Tested-by: Tom St Denis <tom.stdenis@amd.com>
    Reviewed-by: Shaoyun liu  <shaoyun.liu@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex