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Date:   Wed, 3 Jun 2020 13:31:37 +0100
From:   Russell King - ARM Linux admin <linux@armlinux.org.uk>
To:     Andrew Lunn <andrew@lunn.ch>
Cc:     Thomas Bogendoerfer <tbogendoerfer@suse.de>,
        "David S. Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH net] net: mvpp2: Enable autoneg bypass for
 1000BaseX/2500BaseX ports
Message-ID: <20200603123137.GZ1551@shell.armlinux.org.uk>
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On Tue, Jun 02, 2020 at 11:50:16PM +0100, Russell King - ARM Linux admin wrote:
> On Fri, May 29, 2020 at 06:33:40PM +0200, Andrew Lunn wrote:
> > Given the current code, you cannot. Now we understand the
> > requirements, we can come up with some ideas how to do this properly.
> 
> Okay, I've been a little quiet because of sorting out the ARM tree
> for merging with Linus (now done) and I've been working on a solution
> to this problem.
> 
> The good news is, I have an implementation in phylink to use the sync
> status reported from a PCS, and to appropriately enable sync status
> reporting.  I'm quite nervous about having that enabled as a matter of
> routine as I've seen some Marvell hardware end up with interrupt storms
> from it - presumably due to noise pickup on the serdes lines being
> interpreted as an intermittently valid signal.

Yes, as expected - though not quite a storm - I'm seeing:

[root@buildroot ~]# dmesg |grep 'eno2:' | wc -l
1604
[root@buildroot ~]# dmesg |grep 'eno2: mac link down' | wc -l
1598
[root@buildroot ~]# cat /proc/uptime
68868.10 137231.62

Similar happens with mvpp2 hardware - for Marvell's older mvpp2x driver,
I had to disable the AN bypass bit:

    net: marvell: mvpp2x: avoid link status flood

    eth2 on the Macchiatobin board floods the system with link status
    interrupts whilethe link is down.  This appears to be caused by the
    AN bypass logic causing spurious link status change interrupts,
    despite the port status register indicating that the link remains
    down.

    Avoid this by not setting the AN bypass bit for SGMII links.

    Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

So, it looks like a different approach will be needed, since having a
system flooded with unnecessary interrupts is obviously bad.  This
isn't limited to just Marvell mvneta and mvpp2, I think Chris at ZII
has reported a similar behaviour on his boards with noise inducing
serdes sync/link events.

Hmm.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC for 0.8m (est. 1762m) line in suburbia: sync at 13.1Mbps down 424kbps up