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[23.128.96.18]) by mx.google.com with ESMTP id n22si6407016ejd.119.2020.06.06.21.16.04; Sat, 06 Jun 2020 21:16:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@brainfault-org.20150623.gappssmtp.com header.s=20150623 header.b=CtfasOda; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726068AbgFGEOQ (ORCPT + 99 others); Sun, 7 Jun 2020 00:14:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725798AbgFGEOP (ORCPT ); Sun, 7 Jun 2020 00:14:15 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3304C08C5C3 for ; Sat, 6 Jun 2020 21:14:13 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id r15so13106310wmh.5 for ; Sat, 06 Jun 2020 21:14:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=XVc4yhBjX64RmWB7JPsVL5b7vYsNR1j+6MV6XcBMtDw=; b=CtfasOdaLXASDTrfjslQSlb2cqhb29HcfYBxMM5gwUNZwgYhjFVOJJt3EsqsRRj8Mq MPsUtDcpnNJR0Lf2iFnRRD0haPlkB0y2BDkNmMA3zxG+nHPLIiLLMsosbxi8SYy3mOjQ SINXa/N2/2XmgVa8M1cuIZqX1q9TQ+1hdr+Qxoyl+O7U2sM9PfYNmbnk5KUhIXG1wRm9 N6HVew6cfN66BUbc6+MqB98EHNkB1KPb8G7BhL7d4jaq251q+IX1fMMosOyuy5PA1O6a /D6k6s+0y7JYtMzhpsDI8BvoHN3LKwNA8abau/aFJaUjfYMHtWhFZWMwFUmOp/7xhWS9 Xqeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=XVc4yhBjX64RmWB7JPsVL5b7vYsNR1j+6MV6XcBMtDw=; b=Y7tgb1TYPEKR6ywCsEt5P01fJMpAQ7OLZ1XRFmmzRlB29VXzL4WPmt5otUrOJole71 oDPfFTWMseOstEtKXC/aV0EcTm5LILVHHSxGouBnMkeU180ZCobFs096bkjOI8rlFb3U mbf/Xve4eeBqAjVRF+3Pz1bJBwL55l6dDjxpvBQgKBfJHi3JepGWRWPiUE9tild/PcAK N8vHrf+K0Io97I3Rf5Xog51N2J+mnh2ISEMskkl93x8lQcoocJEAdJVjr8J8vYur8rsm JhQXuRxs2A+enqkjSfw8RSDrAkBD0ax5gBpB4TzdWKXzi+NBHVMmcMdE17k1eFSpm0dj V9Gg== X-Gm-Message-State: AOAM532mIj3+kMox9pxvG+mBBMQ/6eDXaHwzknYt0EezgQAB1vvbdktN AYg56vDlNvuNRvrmFvIFnL5T9Ag1q/j+mMSI6AOtSQ== X-Received: by 2002:a1c:1b17:: with SMTP id b23mr9875982wmb.3.1591503251213; Sat, 06 Jun 2020 21:14:11 -0700 (PDT) MIME-Version: 1.0 References: <20200521134544.816918-3-anup.patel@wdc.com> In-Reply-To: From: Anup Patel Date: Sun, 7 Jun 2020 09:43:59 +0530 Message-ID: Subject: Re: [PATCH 2/5] RISC-V: Remove CLINT related code To: Palmer Dabbelt Cc: Anup Patel , Paul Walmsley , Albert Ou , Rob Herring , Daniel Lezcano , Thomas Gleixner , Damien Le Moal , Atish Patra , Alistair Francis , linux-riscv , "linux-kernel@vger.kernel.org List" , devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 5, 2020 at 2:10 AM Palmer Dabbelt wrote: > > On Thu, 21 May 2020 06:45:41 PDT (-0700), Anup Patel wrote: > > We will be having separate CLINT timer driver which will also > > provide CLINT based IPI operations so let's remove CLINT related > > code from arch/riscv directory. > > This will leave the system unbootable, which breaks bisecting. This only affects the NoMMU kernel where userspace FPDPIC work is still in-progress so NoMMU kernel is anyway not 100% complete without upstreamed userspace support. Are you suggesting to squash PATCH2, PATCH3, and PATCH4 for preserving bistability ? Regards, Anup > > > > > Signed-off-by: Anup Patel > > --- > > arch/riscv/include/asm/clint.h | 39 ------------------------------ > > arch/riscv/kernel/Makefile | 2 +- > > arch/riscv/kernel/clint.c | 44 ---------------------------------- > > arch/riscv/kernel/setup.c | 2 -- > > arch/riscv/kernel/smp.c | 1 - > > arch/riscv/kernel/smpboot.c | 1 - > > 6 files changed, 1 insertion(+), 88 deletions(-) > > delete mode 100644 arch/riscv/include/asm/clint.h > > delete mode 100644 arch/riscv/kernel/clint.c > > > > diff --git a/arch/riscv/include/asm/clint.h b/arch/riscv/include/asm/clint.h > > deleted file mode 100644 > > index a279b17a6aad..000000000000 > > --- a/arch/riscv/include/asm/clint.h > > +++ /dev/null > > @@ -1,39 +0,0 @@ > > -/* SPDX-License-Identifier: GPL-2.0 */ > > -#ifndef _ASM_RISCV_CLINT_H > > -#define _ASM_RISCV_CLINT_H 1 > > - > > -#include > > -#include > > - > > -#ifdef CONFIG_RISCV_M_MODE > > -extern u32 __iomem *clint_ipi_base; > > - > > -void clint_init_boot_cpu(void); > > - > > -static inline void clint_send_ipi_single(unsigned long hartid) > > -{ > > - writel(1, clint_ipi_base + hartid); > > -} > > - > > -static inline void clint_send_ipi_mask(const struct cpumask *mask) > > -{ > > - int cpu; > > - > > - for_each_cpu(cpu, mask) > > - clint_send_ipi_single(cpuid_to_hartid_map(cpu)); > > -} > > - > > -static inline void clint_clear_ipi(unsigned long hartid) > > -{ > > - writel(0, clint_ipi_base + hartid); > > -} > > -#else /* CONFIG_RISCV_M_MODE */ > > -#define clint_init_boot_cpu() do { } while (0) > > - > > -/* stubs to for code is only reachable under IS_ENABLED(CONFIG_RISCV_M_MODE): */ > > -void clint_send_ipi_single(unsigned long hartid); > > -void clint_send_ipi_mask(const struct cpumask *hartid_mask); > > -void clint_clear_ipi(unsigned long hartid); > > -#endif /* CONFIG_RISCV_M_MODE */ > > - > > -#endif /* _ASM_RISCV_CLINT_H */ > > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile > > index d8bbd3207100..529cda705cfe 100644 > > --- a/arch/riscv/kernel/Makefile > > +++ b/arch/riscv/kernel/Makefile > > @@ -31,7 +31,7 @@ obj-y += cacheinfo.o > > obj-y += patch.o > > obj-$(CONFIG_MMU) += vdso.o vdso/ > > > > -obj-$(CONFIG_RISCV_M_MODE) += clint.o traps_misaligned.o > > +obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o > > obj-$(CONFIG_FPU) += fpu.o > > obj-$(CONFIG_SMP) += smpboot.o > > obj-$(CONFIG_SMP) += smp.o > > diff --git a/arch/riscv/kernel/clint.c b/arch/riscv/kernel/clint.c > > deleted file mode 100644 > > index 3647980d14c3..000000000000 > > --- a/arch/riscv/kernel/clint.c > > +++ /dev/null > > @@ -1,44 +0,0 @@ > > -// SPDX-License-Identifier: GPL-2.0 > > -/* > > - * Copyright (c) 2019 Christoph Hellwig. > > - */ > > - > > -#include > > -#include > > -#include > > -#include > > -#include > > -#include > > -#include > > - > > -/* > > - * This is the layout used by the SiFive clint, which is also shared by the qemu > > - * virt platform, and the Kendryte KD210 at least. > > - */ > > -#define CLINT_IPI_OFF 0 > > -#define CLINT_TIME_CMP_OFF 0x4000 > > -#define CLINT_TIME_VAL_OFF 0xbff8 > > - > > -u32 __iomem *clint_ipi_base; > > - > > -void clint_init_boot_cpu(void) > > -{ > > - struct device_node *np; > > - void __iomem *base; > > - > > - np = of_find_compatible_node(NULL, NULL, "riscv,clint0"); > > - if (!np) { > > - panic("clint not found"); > > - return; > > - } > > - > > - base = of_iomap(np, 0); > > - if (!base) > > - panic("could not map CLINT"); > > - > > - clint_ipi_base = base + CLINT_IPI_OFF; > > - riscv_time_cmp = base + CLINT_TIME_CMP_OFF; > > - riscv_time_val = base + CLINT_TIME_VAL_OFF; > > - > > - clint_clear_ipi(boot_cpu_hartid); > > -} > > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c > > index 145128a7e560..b07a583bf53b 100644 > > --- a/arch/riscv/kernel/setup.c > > +++ b/arch/riscv/kernel/setup.c > > @@ -18,7 +18,6 @@ > > #include > > #include > > > > -#include > > #include > > #include > > #include > > @@ -76,7 +75,6 @@ void __init setup_arch(char **cmdline_p) > > setup_bootmem(); > > paging_init(); > > unflatten_device_tree(); > > - clint_init_boot_cpu(); > > > > #ifdef CONFIG_SWIOTLB > > swiotlb_init(1); > > diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c > > index 8375cc5970f6..8a23f1eb5400 100644 > > --- a/arch/riscv/kernel/smp.c > > +++ b/arch/riscv/kernel/smp.c > > @@ -17,7 +17,6 @@ > > #include > > #include > > > > -#include > > #include > > #include > > #include > > diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c > > index 5fe849791bf0..a6cfa9842d4b 100644 > > --- a/arch/riscv/kernel/smpboot.c > > +++ b/arch/riscv/kernel/smpboot.c > > @@ -24,7 +24,6 @@ > > #include > > #include > > #include > > -#include > > #include > > #include > > #include