Received: by 2002:a25:683:0:0:0:0:0 with SMTP id 125csp456393ybg; Wed, 10 Jun 2020 05:21:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzWN79bNxLvhgbmb2+/JMoTHAJTY37UYIcv4qkQXDzoEnL8iOZfVwksmpyQPEbEpWUjndvP X-Received: by 2002:aa7:c2c4:: with SMTP id m4mr2137238edp.299.1591791715325; Wed, 10 Jun 2020 05:21:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591791715; cv=none; d=google.com; s=arc-20160816; b=LhG25ZcklYxQc2QBmEuxKLyW0WHl57rBESCwPnKW4PxfpgYxIZHjZk7PWrW05IL+CK 9ti5Ku7FJNWlbI6Xz9meCiJuuq2UyMXIU0X0/zZxzfjc7mJsFhgLus091jzGlEPyO1Yl hvVG8lCOMQ2owNFkSLR/ADi+IdfLxZh0gRROc9z6IZqasl1zNoVCOxrRp4XYToafcAA1 U30DH/k9nFcM5VXBNOPAZcx2yh1RVJRIeBd9NSrGoZibnMXaMlXe2TTJO3YY4QeJd1dU om5hY57qYK4AOj6ivGxaVNabxObxBLKG7jnC3juExPECb6n8LimeFBbSG66G58xzxn8P kD+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :ironport-sdr:ironport-sdr; bh=2lgHyRgvmaolqkbr9Rk2yKvReT0TSN8+zPFeAq/taYM=; b=HtIp467xuI8ay78U8zW0F8C1TkB20fN++6/VaahhWRlQDZSq7NTVj33mXTQtz2YEdy dzf/Kr5prnWw4IlIRfOGQCna+sMCvvfhiM3lItGTbTxNKdAgh2ZhK9dkiyaWgDR2lOzy MqlU4pTXI7E49j4ldecQLI5YN4pGSwWWN7zDr16N+rIpj+3ISrRUZPkmlpyNzRujhyZa qisWV5xnAVp/PO4MzqnZToeQfeXSam5XZF6y4jn/qaWV7Dpcl86S7aV1hlRempSxwqVZ 9KUN/sV2Ovm1t9D36aIQduHrCJHG1z7xAJF/15yjD6noj4KGimOPWCh5t9xqT2n+hzXE Q4zw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q21si12391742edw.46.2020.06.10.05.21.31; Wed, 10 Jun 2020 05:21:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728977AbgFJMTf (ORCPT + 99 others); Wed, 10 Jun 2020 08:19:35 -0400 Received: from mga07.intel.com ([134.134.136.100]:42305 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728540AbgFJMTf (ORCPT ); Wed, 10 Jun 2020 08:19:35 -0400 IronPort-SDR: 3syKbqmVcKn19g8fhwDnbCBDjWXMLOZF8nQcVFYR9buNqI2TgWtAdmjBBDJ3T6l+dsMpQUFZl4 YbWU8ScOLvoQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2020 05:19:34 -0700 IronPort-SDR: iQnS+2TeSpXWWy9Frd9LkLSM0b66DreyvmOvysbvmcLDc1I9YpoQAV3Sx6hGwjO1bkt3tENwlH 3LP1GlgHJvUA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,495,1583222400"; d="scan'208";a="473405887" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by fmsmga005.fm.intel.com with ESMTP; 10 Jun 2020 05:19:31 -0700 From: Amireddy Mallikarjuna reddy To: dmaengine@vger.kernel.org, vkoul@kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org Cc: linux-kernel@vger.kernel.org, andriy.shevchenko@intel.com, chuanhua.lei@linux.intel.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, malliamireddy009@gmail.com, Amireddy Mallikarjuna reddy Subject: [PATCH 0/2] Add Intel LGM soc DMA support Date: Wed, 10 Jun 2020 20:17:54 +0800 Message-Id: X-Mailer: git-send-email 2.11.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DMA controller driver for Lightning Mountain(LGM) family of SoCs. The main function of the DMA controller is the transfer of data from/to any DPlus compliant peripheral to/from the memory. A memory to memory copy capability can also be configured. This ldma driver is used for configure the device and channnels for data and control paths. These controllers provide DMA capabilities for a variety of on-chip devices such as SSC, HSNAND and GSWIP. ------------- Future Plans: ------------- LGM SOC also supports Hardware Memory Copy engine. The role of the HW Memory copy engine is to offload memory copy operations from the CPU. Amireddy Mallikarjuna reddy (2): dt-bindings: dma: Add bindings for intel LGM SOC Add Intel LGM soc DMA support. .../devicetree/bindings/dma/intel,ldma.yaml | 428 +++++ drivers/dma/Kconfig | 2 + drivers/dma/Makefile | 1 + drivers/dma/lgm/Kconfig | 9 + drivers/dma/lgm/Makefile | 2 + drivers/dma/lgm/lgm-dma.c | 1951 ++++++++++++++++++++ 6 files changed, 2393 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/intel,ldma.yaml create mode 100644 drivers/dma/lgm/Kconfig create mode 100644 drivers/dma/lgm/Makefile create mode 100644 drivers/dma/lgm/lgm-dma.c -- 2.11.0