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Date:   Wed, 10 Jun 2020 10:35:20 +0100
From:   Marc Zyngier <maz@kernel.org>
To:     Daniel Palmer <daniel@0x0f.com>
Cc:     k@japko.eu, tim.bird@sony.com, devicetree@vger.kernel.org,
        Daniel Palmer <daniel@thingy.jp>,
        Rob Herring <robh+dt@kernel.org>,
        Russell King <linux@armlinux.org.uk>,
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        Linus Walleij <linus.walleij@linaro.org>,
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        Lubomir Rintel <lkundrak@v3.sk>,
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Subject: Re: [PATCH v2 3/5] ARM: mstar: Add infinity/mercury series dtsi
In-Reply-To: <20200610090421.3428945-4-daniel@0x0f.com>
References: <20191014061617.10296-2-daniel@0x0f.com>
 <20200610090421.3428945-4-daniel@0x0f.com>
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Daniel,

On 2020-06-10 10:04, Daniel Palmer wrote:
> Adds initial dtsi for the base MStar ARMv7 SoCs, family dtsis for 
> infinity
> and mercury families, and then some chip level dtsis for chips in those
> families.
> 
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
> ---
>  MAINTAINERS                              |  3 +
>  arch/arm/boot/dts/infinity-msc313.dtsi   | 14 +++++
>  arch/arm/boot/dts/infinity.dtsi          | 10 ++++
>  arch/arm/boot/dts/infinity3-msc313e.dtsi | 14 +++++
>  arch/arm/boot/dts/infinity3.dtsi         | 10 ++++
>  arch/arm/boot/dts/mercury5-ssc8336n.dtsi | 14 +++++
>  arch/arm/boot/dts/mercury5.dtsi          | 10 ++++
>  arch/arm/boot/dts/mstar-v7.dtsi          | 71 ++++++++++++++++++++++++
>  8 files changed, 146 insertions(+)
>  create mode 100644 arch/arm/boot/dts/infinity-msc313.dtsi
>  create mode 100644 arch/arm/boot/dts/infinity.dtsi
>  create mode 100644 arch/arm/boot/dts/infinity3-msc313e.dtsi
>  create mode 100644 arch/arm/boot/dts/infinity3.dtsi
>  create mode 100644 arch/arm/boot/dts/mercury5-ssc8336n.dtsi
>  create mode 100644 arch/arm/boot/dts/mercury5.dtsi
>  create mode 100644 arch/arm/boot/dts/mstar-v7.dtsi

[...]

> diff --git a/arch/arm/boot/dts/mstar-v7.dtsi 
> b/arch/arm/boot/dts/mstar-v7.dtsi
> new file mode 100644
> index 000000000000..0fccc4ca52a4
> --- /dev/null
> +++ b/arch/arm/boot/dts/mstar-v7.dtsi
> @@ -0,0 +1,71 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 thingy.jp.
> + * Author: Daniel Palmer <daniel@thingy.jp>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	interrupt-parent = <&gic>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a7";
> +			reg = <0x0>;
> +		};
> +	};
> +
> +	arch_timer {
> +		compatible = "arm,armv7-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
> +				| IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
> +				| IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
> +				| IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
> +				| IRQ_TYPE_LEVEL_LOW)>;
> +		clock-frequency = <6000000>;

This is 2020, and not 2012 anymore. The frequency should be set
by your favourite bootloader.

> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a7-pmu";
> +		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	soc: soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		gic: interrupt-controller@16001000 {
> +			compatible = "arm,cortex-a7-gic";
> +			#interrupt-cells = <3>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			interrupt-controller;
> +			reg = <0x16001000 0x1000>,
> +			      <0x16002000 0x1000>;

The GICC region is likely to be 8kB, and not 4kB.
Missing GICH and GICV regions, as well as the maintenance interrupt.

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...