Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
In-Reply-To: <3ac34bd7-bc5b-bc04-99ba-8ba3c5a9a691@codeaurora.org>
References: <1589707344-8871-1-git-send-email-tdas@codeaurora.org> <1589707344-8871-5-git-send-email-tdas@codeaurora.org> <159054904061.88029.1394425232497625411@swboyd.mtv.corp.google.com> <3ac34bd7-bc5b-bc04-99ba-8ba3c5a9a691@codeaurora.org>
Subject: Re: [PATCH v2 4/4] clk: qcom: lpass: Add support for LPASS clock controller for SC7180
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     David Brown <david.brown@linaro.org>,
        Rajendra Nayak <rnayak@codeaurora.org>,
        linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        Andy Gross <agross@kernel.org>, devicetree@vger.kernel.org,
        robh@kernel.org, robh+dt@kernel.org
To:     Michael Turquette <mturquette@baylibre.com>,
        Taniya Das <tdas@codeaurora.org>
Date:   Wed, 10 Jun 2020 18:06:42 -0700
Message-ID: <159183760269.242598.3005455698894049563@swboyd.mtv.corp.google.com>
User-Agent: alot/0.9
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Quoting Taniya Das (2020-06-10 10:11:49)
> On 5/27/2020 8:40 AM, Stephen Boyd wrote:
> > Quoting Taniya Das (2020-05-17 02:22:24)
> >> +       if (ret)
> >> +               return ret;
> >> +
> >> +       lpass_core_cc_sc7180_regmap_config.name =3D "lpass_core_cc";
> >> +       regmap =3D qcom_cc_map(pdev, &lpass_core_cc_sc7180_desc);
> >> +       if (IS_ERR(regmap))
> >> +               return PTR_ERR(regmap);
> >> +
> >> +       /*
> >> +        * Keep the CLK always-ON
> >=20
> > Why? Presumably to make sure we can access the lpass sysnoc path all the
> > time?
> >=20
>=20
> This is an always ON clock from HW, just making sure to keep it enabled.

I'm not following. Hardware says it must always be enabled? If it isn't
enabled is it even possible to write this register?

>=20
> >> +        * LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK
> >> +        */
> >> +       regmap_update_bits(regmap, 0x24000, BIT(0), BIT(0));
> >> +