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From:   Ravi Kumar Bokka <rbokka@codeaurora.org>
To:     Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
        Rob Herring <robh+dt@kernel.org>
Cc:     linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        rnayak@codeaurora.org, saiprakash.ranjan@codeaurora.org,
        dhavalp@codeaurora.org, mturney@codeaurora.org,
        sparate@codeaurora.org, c_rbokka@codeaurora.org,
        mkurumel@codeaurora.org, Ravi Kumar Bokka <rbokka@codeaurora.org>
Subject: [RFC v2 1/3] dt-bindings: nvmem: Add devicetree bindings for qfprom-efuse
Date:   Thu, 11 Jun 2020 15:18:00 +0530
Message-Id: <1591868882-16553-2-git-send-email-rbokka@codeaurora.org>
In-Reply-To: <1591868882-16553-1-git-send-email-rbokka@codeaurora.org>
References: <1591868882-16553-1-git-send-email-rbokka@codeaurora.org>
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This patch adds dt-bindings document for qfprom-efuse controller.

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
---
 .../devicetree/bindings/nvmem/qfprom.yaml          | 52 ++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nvmem/qfprom.yaml

diff --git a/Documentation/devicetree/bindings/nvmem/qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qfprom.yaml
new file mode 100644
index 0000000..7c8fc31
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/qfprom.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/qfprom.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies Inc, QFPROM Efuse bindings
+
+maintainers:
+  - Ravi Kumar Bokka <rbokka@codeaurora.org>
+
+allOf:
+  - $ref: "nvmem.yaml#"
+
+properties:
+  compatible:
+    enum:
+      - qcom,qfprom
+
+  reg:
+    maxItems: 3
+
+required:
+   - compatible
+   - reg
+   - reg-names
+   - clocks
+   - clock-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
+
+    qfprom@780000 {
+	compatible = "qcom,qfprom";
+	reg = <0 0x00780000 0 0x7a0>,
+	      <0 0x00782000 0 0x100>,
+	      <0 0x00784000 0 0x8ff>;
+	reg-names = "raw", "conf", "corrected";
+	clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
+	clock-names = "secclk";
+
+	qusb2p_hstx_trim: hstx-trim-primary@25b {
+		reg = <0x25b 0x1>;
+		bits = <1 3>;
+	};
+    };
+
+    &qfprom {
+        vcc-supply = <&vreg_l11a_1p8>;
+    };
+
-- 
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