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[23.128.96.18]) by mx.google.com with ESMTP id dk10si2394678ejb.554.2020.06.11.10.34.20; Thu, 11 Jun 2020 10:34:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@0x0f.com header.s=google header.b=IT02dr8G; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726976AbgFKOTn (ORCPT + 99 others); Thu, 11 Jun 2020 10:19:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726936AbgFKOTn (ORCPT ); Thu, 11 Jun 2020 10:19:43 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06829C08C5C2 for ; Thu, 11 Jun 2020 07:19:41 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id j198so7075084wmj.0 for ; Thu, 11 Jun 2020 07:19:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=dnKHXPEH1ozj37XOHtlpuuX/tbRfdpMEjZIEpqlLX6M=; b=IT02dr8GiskF5HGBwCOY84YSjJ5fu38NZHDoVPW7pUp3oEhZJwUiNVkPodr7wSVMTK kkv60uU6Ss3TLFgX8lqs4zDFWnQV0tQ8z7co8MsQb9sDFhmYGg1dvzFmRsGLexWwl3ON Cckjui3jfLAUmj6YPXOey9tYqH3IvmrSyQN68= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=dnKHXPEH1ozj37XOHtlpuuX/tbRfdpMEjZIEpqlLX6M=; b=tIDXtqzgrFWr8VSdInjiVhEOFpzo7BOI0lHVlCTjo2CjTRhM3PYXInRRYGoL5tCFJm FU5Vi7x6idypx9PJjiZBocs3drugHoJpBy6f2RZ7Wvxr8oNTGqxYJXxqxTheYBrV4dt1 V4rjC0wbLB1RPM2CuWrWqqruw6/9op+5ZXDdjX6x00tKeM9c+/avuDV/xIgfJvwoEFld Z8bV727Vu6/jrURasR7hKSs7YhZ9RqjqwsrKF8d0wrid2hcBPtT3m94Zn0yWC4iItlAM S3Azk9GCgE7bscioXbBKOB96Aedwf2GSv8+JF3/woZKiUwGeLSx+LrtXyk/Pp+R1b6Qr 4L5w== X-Gm-Message-State: AOAM530Lo0AD9Fv7AGICw3ynlxP/pT+U+d0PtNIGLK+KzCbLi1fcsZmI W4RvbNpXVSM2Dk9MbbiU9d25cO9aBCqP7lOb1uGBBw== X-Received: by 2002:a1c:491:: with SMTP id 139mr7954685wme.99.1591885179520; Thu, 11 Jun 2020 07:19:39 -0700 (PDT) MIME-Version: 1.0 References: <20191014061617.10296-2-daniel@0x0f.com> <20200610090421.3428945-4-daniel@0x0f.com> In-Reply-To: From: Daniel Palmer Date: Thu, 11 Jun 2020 23:19:23 +0900 Message-ID: Subject: Re: [PATCH v2 3/5] ARM: mstar: Add infinity/mercury series dtsi To: =?UTF-8?Q?Andreas_F=C3=A4rber?= Cc: Krzysztof Adamski , tim.bird@sony.com, devicetree@vger.kernel.org, Daniel Palmer , Rob Herring , Russell King , Sam Ravnborg , Linus Walleij , Heiko Stuebner , Maxime Ripard , Lubomir Rintel , Stephan Gerhold , Mark Brown , allen , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Corbet , Arnd Bergmann , Andrew Morton , Doug Anderson , Benjamin Gaignard , Gregory Fong , Bartosz Golaszewski , Masahiro Yamada , Nick Desaulniers , Will Deacon , Nathan Huckleberry , Nathan Chancellor , Marc Zyngier , Ard Biesheuvel , linux-arm-kernel , linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andreas, On Thu, 11 Jun 2020 at 22:39, Andreas F=C3=A4rber wrote: > Can you split this up into three parts for easier review? Understood. Will do. > 2019-2020? Check elsewhere. The patches are originally from 2019. I'll update everything. > > + * Author: Daniel Palmer > > + */ > > + > > +#include "infinity.dtsi" > > + > > +/ { > > + memory { > > + device_type =3D "memory"; > > + reg =3D <0x20000000 0x4000000>; > > The memory node needs to become memory@20000000 then. > > > + }; > > I take it, this RAM is integrated? Maybe add some explanation of what > this file is Yes. The memory is integrated and the size depends on the specific chips so the memory node is at the chip level dtsi and not the board level. > > +}; > > diff --git a/arch/arm/boot/dts/infinity.dtsi b/arch/arm/boot/dts/infini= ty.dtsi > > new file mode 100644 > > index 000000000000..25d379028689 > > --- /dev/null > > +++ b/arch/arm/boot/dts/infinity.dtsi > > @@ -0,0 +1,10 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2019 thingy.jp. > > + * Author: Daniel Palmer > > + */ > > + > > +#include "mstar-v7.dtsi" > > + > > +/ { > > +}; > > What do you intend to add here? Is it really needed? (same below) The specific nodes will go into there. This is mostly an artefact of splitt= ing the device trees out of a more developed tree. > > new file mode 100644 > > index 000000000000..cf5f18a07835 > > --- /dev/null > > +++ b/arch/arm/boot/dts/infinity3.dtsi > > @@ -0,0 +1,10 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2019 thingy.jp. > > + * Author: Daniel Palmer > > + */ > > + > > +#include "infinity.dtsi" > > + > > +/ { > > +}; > > Don't you anticipate incompatibilities between infinity and infinity3, > i.e., things you don't want to inherit? Seems a bit optimistic. You can > of course overwrite properties, but deleting is more difficult. In my tree with drivers for the rest of the hardware it hasn't been a probl= em. So far I've found infinity, infinity2, infinity3, infinity5 and infinity6 chips. The memory map for them is almost identical and the changes are adding in more copies of things like DMA controllers, extra clock blocks etc. Having infinity.dtsi as the base for the newer versions should avoid having duplication of nodes that aren't common on the mstar armv7 level but are common to the infinity subtypes. There are two good examples of this: For infinity? the USB and SD controllers are at the same place for all of the chips I've found so far. Unfortunately, despite using the same IP block and the same driver those blocks are in different places in the mercury5. At the moment with all of the infinity chips pulling in infinity.dtsi those nodes are only in infinity.dtsi and mercury5.dtsi. If infinity?.dtsi are all stacked on top of the mstarv7.dtsi base then there will be a number of copies of the same nodes. > > diff --git a/arch/arm/boot/dts/mercury5.dtsi b/arch/arm/boot/dts/mercur= y5.dtsi > > new file mode 100644 > > index 000000000000..25d379028689 > > --- /dev/null > > +++ b/arch/arm/boot/dts/mercury5.dtsi > > @@ -0,0 +1,10 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2019 thingy.jp. > > + * Author: Daniel Palmer > > + */ > > + > > +#include "mstar-v7.dtsi" > > + > > +/ { > > +}; > > diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-= v7.dtsi > > new file mode 100644 > > index 000000000000..0fccc4ca52a4 > > --- /dev/null > > +++ b/arch/arm/boot/dts/mstar-v7.dtsi > > So this is the only file starting with mstar. Have you thought about > prefixing infinity/mercury, so that they're grouped together? I have been thinking about that. I didn't see any other dts in arm that had the vendor as a prefix though. With arm64 everything is in per vendor subdirectories to achieve the same thing. > > + }; > > + > > + pm_uart: uart@1f221000 { > > + compatible =3D "ns16550a"; > > + reg =3D <0x1f221000 0x100>; > > + reg-shift =3D <3>; > > + clock-frequency =3D <172000000>; > > + status =3D "disabled"; > > + }; > > If you have any decent manuals for these SoCs, Everything so far has been reverse engineered from an old 3.18 kernel, poking with a multimeter etc. I wish I had a decent manual. > I suggest to check whether there are any internal buses that you may > want to model as simple-bus for grouping. In-tree examples include meson > and recently merged rtd1195 - it affects the reg addresses and unit addre= sses via > suitable ranges mappings. There is a bridge that is between the CPU and the peripheral registers that doesn't quite fit simple-bus (from what I remember it needs a clk). My plan was to introduce the thin driver for that bus (it just consumes the= clks it needs so they don't get disabled at the moment) after introducing the clk support. Thanks, Daniel