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[23.128.96.18]) by mx.google.com with ESMTP id jz17si2455368ejb.243.2020.06.11.11.51.16; Thu, 11 Jun 2020 11:51:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@0x0f.com header.s=google header.b=FwBN+sIO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728228AbgFKO1Q (ORCPT + 99 others); Thu, 11 Jun 2020 10:27:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726657AbgFKO1Q (ORCPT ); Thu, 11 Jun 2020 10:27:16 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6C39C08C5C1 for ; Thu, 11 Jun 2020 07:27:15 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id c71so5149943wmd.5 for ; Thu, 11 Jun 2020 07:27:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=9PTMI4AzXbLxjyyfz+xfdpQHe4hbBWsXmsCFiQIKN4U=; b=FwBN+sIO4TrTpP0kISN3kEu0krnuRDrBMvQaELuZn2dafIWWIy3mCsH4FnnW14hbhE mQZvr+O1MMO1HbLLkF3esMZtzen5E4PSL/AFedMg9N7ZvIJHmtFJqWaEOL1D+FWBJpdk ++BzE/BZLtUb84uvG5wlSGRetmJXlxgLzcf6Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=9PTMI4AzXbLxjyyfz+xfdpQHe4hbBWsXmsCFiQIKN4U=; b=ooRAbju7FFFlakNNNgthb1jffHhuql834gE+izeiVkaKR4w0KYB/jukR7HuFR0xJKN HHSAHiqhOostGTCVZfejd4wTG0i7PtaTH1HupVuriK4UGju/JXAlIjnZ+NttvEO+WtfM Z2kJxyYG7zhEEuUU60aa1TdhB+vITBOa6x+2z9GCOTxo9tkTih18na7fGA4+vNmxwJuQ 0ngHWnPgn4eIU9SuSMw5RCVki2V3hba4alsIbN7vzBC2aIpqwzK4ZeOAP3BVmoWZxsZ9 eSOoxxgQJ9VGifmOYucDDFGjwPxFYZkY/9htmcXyAjaCUQMp9L1npcwVyB9WFL4MuWez ZkMA== X-Gm-Message-State: AOAM532h6+0yBczBjWr8kY+Ds91RpLOPnOrU7Qs8rMZalIx3LRX+6pfh ExLq9ItpJrjnrMUJMI7+icqpDXtIeTsTMHbaySTlMA== X-Received: by 2002:a1c:7206:: with SMTP id n6mr8751619wmc.4.1591885634606; Thu, 11 Jun 2020 07:27:14 -0700 (PDT) MIME-Version: 1.0 References: <20191014061617.10296-2-daniel@0x0f.com> <20200610090421.3428945-5-daniel@0x0f.com> <42aa9e03-3fcc-a602-40db-cfbddef36b34@suse.de> In-Reply-To: <42aa9e03-3fcc-a602-40db-cfbddef36b34@suse.de> From: Daniel Palmer Date: Thu, 11 Jun 2020 23:26:59 +0900 Message-ID: Subject: Re: [PATCH v2 4/5] ARM: mstar: Add dts for msc313(e) based BreadBee boards To: =?UTF-8?Q?Andreas_F=C3=A4rber?= Cc: Krzysztof Adamski , tim.bird@sony.com, devicetree@vger.kernel.org, Daniel Palmer , Rob Herring , Russell King , Sam Ravnborg , Linus Walleij , Heiko Stuebner , Stephan Gerhold , Lubomir Rintel , Maxime Ripard , Mark Brown , allen , Mauro Carvalho Chehab , "David S. Miller" , Jonathan Corbet , Greg Kroah-Hartman , Arnd Bergmann , Mike Rapoport , Andrew Morton , Doug Anderson , Benjamin Gaignard , Gregory Fong , Bartosz Golaszewski , Masahiro Yamada , Nick Desaulniers , Nathan Chancellor , Ard Biesheuvel , Nathan Huckleberry , Marc Zyngier , linux-arm-kernel , linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andreas, On Thu, 11 Jun 2020 at 22:45, Andreas F=C3=A4rber wrote: > > + compatible =3D "thingyjp,breadbee-crust", "mstar,infinity"; > > + > > + aliases { > > + serial0 =3D &pm_uart; > > + }; > > + > > + chosen { > > + stdout-path =3D "serial0:115200n8"; > > + }; > > +}; > > + > > +&pm_uart { > > + status =3D "okay"; > > Might this be a more suited place for temporary clock-frequency? For > lack of clk driver it would seem to depend on the board's bootloader > pre-configuring it rather than being a default of the SoC. For all of the chips so far their second stage bootloader always turns on a PLL and reconfigures the pm_uart clock to use a 172MHz tap from that PLL right at the start of the boot process before u-boot is started. The new u-boot SPL I'm working on to replace that loader follows that convention. Once the clk parts are in it should be possible to pull out the fixed frequency and replace it with a proper handle to that PLL tap. Basically it's not documented anywhere except the assembly but the convention for these chips is to use the 172MHz clock for the uart pretty soon after power on so it made sense to have it in one place. Thanks, Daniel