Received: by 2002:a25:683:0:0:0:0:0 with SMTP id 125csp246596ybg; Thu, 11 Jun 2020 23:53:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzIYdrb9CBpGHQwtWvF96LlvHopw3ZvSb2UBSrHqM7SAE6gJrAce+XjXV6nOTQc/PXAFwki X-Received: by 2002:a17:906:528b:: with SMTP id c11mr11535074ejm.407.1591944802581; Thu, 11 Jun 2020 23:53:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591944802; cv=none; d=google.com; s=arc-20160816; b=u9J6KAV6eF2wV4+LJzGJBK8009B0kIADcsEdTPl7bqCI/VUw8aWkUyOlJUSM3Pr9N6 nHTEUXUzy1xq7FVFb0egGBcLYhoONb+FHtRzZTRpEDe7aTJwLgMub/Zq7FZ3AFZFNMRf e/6ZEAnl7MQ2G/IXp8gEeURYboQ/rv40vIBcDLKuSRpQia5SEidTWpkQGimOSe+QpULg a2wGaScFznR5rRuLUNXznXsGHgEgqPXDrOKb/DOdeNcQlAwbuYpvUlgZL5+CgvNFrVtU sdQTzSOZhMFr/ojvwk7OSvWdOIhSy2ILzbfNR6NvvfxMKeq/sKvvj7KO/SCsv4Ok6jJP bfgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:to:from; bh=setoIBPklkoinztRWsnGbp4e2P6/swU+M6PaxZ5+yDU=; b=sh8W2SAuY5fYP0UaIVFHPQAx2c/PlUzIIRHLjdKyeNGu7Yx9lItwOD+QZ+asQVdy8G OY4wTjAgzvuVGABIesLMdqZsuLMVDqLQ8b3UChUPBCY7+Q5FDtvsCTQpmCuitXdr76nS Lq7YIv1xZpe3iRDMg61lYjWUf/9SONseLFyOOgiy6C+LEmuADHNDBbMGrhVXF0YQtRSa xf5P4Uwy4SFJGvwfOOEUttQ9Nk63SIP+ObDcaKVgNglHjvKoxBJGIaA76KI8B2vgqe8D 7owR0mAFvPySetT8a0a7K0qHE+81IP3Lgw0K8AfNIayFtsI2urbGGw6oAaYO9MFGhlXR Zy0A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y14si3120905edu.550.2020.06.11.23.52.59; Thu, 11 Jun 2020 23:53:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726610AbgFLGuA (ORCPT + 99 others); Fri, 12 Jun 2020 02:50:00 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:29074 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726290AbgFLGuA (ORCPT ); Fri, 12 Jun 2020 02:50:00 -0400 Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 11 Jun 2020 23:50:00 -0700 Received: from sivaprak-linux.qualcomm.com ([10.201.3.202]) by ironmsg05-sd.qualcomm.com with ESMTP; 11 Jun 2020 23:49:57 -0700 Received: by sivaprak-linux.qualcomm.com (Postfix, from userid 459349) id 8D4322187F; Fri, 12 Jun 2020 12:19:55 +0530 (IST) From: Sivaprakash Murugesan To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, peter.ujfalusi@ti.com, sivaprak@codeaurora.org, boris.brezillon@collabora.com, architt@codeaurora.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 2/2] mtd: rawnand: qcom: set BAM mode only if not set already Date: Fri, 12 Jun 2020 12:19:49 +0530 Message-Id: <1591944589-14357-3-git-send-email-sivaprak@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591944589-14357-1-git-send-email-sivaprak@codeaurora.org> References: <1591944589-14357-1-git-send-email-sivaprak@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver is set by writing BAM_MODE_EN bit on NAND_CTRL register. NAND_CTRL is an operational register and in BAM mode operational registers are read only. So, before writing into NAND_CTRL register check if BAM mode is already enabled by bootloader, and set BAM mode only if it is not set already. Signed-off-by: Sivaprakash Murugesan --- [V3] * Changed commit message to give a small info about BAM drivers/mtd/nand/raw/qcom_nandc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index e0c55bb..4827edd 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2784,7 +2784,14 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) /* enable ADM or BAM DMA */ if (nandc->props->is_bam) { nand_ctrl = nandc_read(nandc, NAND_CTRL); - nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); + /* NAND_CTRL is an operational registers, and CPU + * access to operational registers are read only + * in BAM mode. So update the NAND_CTRL register + * only if it is not in BAM mode. In most cases BAM + * mode will be enabled in bootloader + */ + if (!(nand_ctrl | BAM_MODE_EN)) + nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); } else { nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN); } -- 2.7.4