Received: by 2002:a25:683:0:0:0:0:0 with SMTP id 125csp280397ybg; Fri, 12 Jun 2020 01:04:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzP4WUiTu2+uojt3UuGAERL4sznSAGxvo4lJ8WRXxe9QQhDU/DnRpwcMWDlkNr8GPAuGL00 X-Received: by 2002:a05:6402:158b:: with SMTP id c11mr10560742edv.29.1591949042195; Fri, 12 Jun 2020 01:04:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591949042; cv=none; d=google.com; s=arc-20160816; b=FU0m9Ce5HlDrEUpnysWoB622SUbwy6w7VGRrZ3T3yC9UcFp8Em1Ix5cf2r2EeFJ91B BoFbpV0rx05JKlTrCMbdM8I4S2P/AWtuAwt/rJOPGDZwukdKC5Td4rF9+lmVmrpyVpxo GJGe3nilCRU8IvsUyOkA91Q2ofTo1Z45EHKitQSlCAhjuEtoXwWvplqJRgrYysOVVmzx 4VAoLBEBm0HLBbFhqpR3Td24vdyf9suieksXAzpzj9FNn7s0OqqYNxv9RdYB28z+PJcH uHVq4RIAVDzaAMuq9HI/CUzOt2ofoS9Fgu9uSGypfRq46YVUNq1I64qDz8ppwtQAPCA/ ObEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:to:from; bh=uAeDQvYzmHWajjnkIi52WM6VZ7thJhKoQuvgOCsw5DY=; b=H4LQRgUhX68vgILOwXJ0+DtbRmK2SlJydKUxUJcgNcFzkaKLSCbZUxcDaQ1bqwIClC h6NGC9e9nV1MSI22Ql503/qZAKioGMpJ9JrJQRjE22e+A01R9o0b7+b60j69LAj54sOg iJwV3tT6T97KeTKIjMctkTqPCLsNTNmg+RqlnTHZalgYWhjDG7kadm+rd3L+qh4uxdxa RPEk0iKxi7SAiCxzh5shPl+EtZExhi4fORED7Ekjky2w9m3KuWRfBKNOeR0k1/N+2EMH Ey8WkLS3mYBnI/vaj+oudn8WPTSIF9YUSHuDrUiDYOLyZuZgfmI0ZDrtoMOmfpwB5xlJ 2JcA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp14si4431516ejc.412.2020.06.12.01.03.39; Fri, 12 Jun 2020 01:04:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726385AbgFLH6g (ORCPT + 99 others); Fri, 12 Jun 2020 03:58:36 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:10922 "EHLO alexa-out-sd-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726262AbgFLH6g (ORCPT ); Fri, 12 Jun 2020 03:58:36 -0400 Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 12 Jun 2020 00:58:25 -0700 Received: from sivaprak-linux.qualcomm.com ([10.201.3.202]) by ironmsg-SD-alpha.qualcomm.com with ESMTP; 12 Jun 2020 00:58:23 -0700 Received: by sivaprak-linux.qualcomm.com (Postfix, from userid 459349) id CE32321880; Fri, 12 Jun 2020 13:28:21 +0530 (IST) From: Sivaprakash Murugesan To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, peter.ujfalusi@ti.com, sivaprak@codeaurora.org, boris.brezillon@collabora.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V4 2/2] mtd: rawnand: qcom: set BAM mode only if not set already Date: Fri, 12 Jun 2020 13:28:16 +0530 Message-Id: <1591948696-16015-3-git-send-email-sivaprak@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591948696-16015-1-git-send-email-sivaprak@codeaurora.org> References: <1591948696-16015-1-git-send-email-sivaprak@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver is set by writing BAM_MODE_EN bit on NAND_CTRL register. NAND_CTRL is an operational register and in BAM mode operational registers are read only. So, before enabling BAM mode by writing the NAND_CTRL register, check if BAM mode was already enabled by the bootloader, and enable BAM mode only if it is not enabled already. Signed-off-by: Sivaprakash Murugesan --- drivers/mtd/nand/raw/qcom_nandc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 78b5f21..a3ef428 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2784,7 +2784,14 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) /* enable ADM or BAM DMA */ if (nandc->props->is_bam) { nand_ctrl = nandc_read(nandc, NAND_CTRL); - nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); + /* NAND_CTRL is an operational registers, and CPU + * access to operational registers are read only + * in BAM mode. So update the NAND_CTRL register + * only if it is not in BAM mode. In most cases BAM + * mode will be enabled in bootloader + */ + if (!(nand_ctrl | BAM_MODE_EN)) + nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); } else { nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN); } -- 2.7.4