Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp193462ybt; Sat, 13 Jun 2020 01:16:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJze0AOEB7YQGYYFoViCQKeO4QUy5qrA8dtKjgyNH467KMpNsAj5cmCpM9pPJpQFWqGmYMtI X-Received: by 2002:a17:906:d043:: with SMTP id bo3mr16096515ejb.409.1592036193937; Sat, 13 Jun 2020 01:16:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592036193; cv=none; d=google.com; s=arc-20160816; b=UNqLs5zz6XeT8tmhpnzxaxxUWpK+bH3BH/vnL+E+ivnelPEQvvq+asrzv7HbFg4ipn 0lsyhvBi7fghXBWIuMWmnnzQ4RN1sjzf00pj/sy0F4WJUwj9FOAWonczG6B6P9JU6hm4 0roQXDNanBVP1MnI2rY6AHhNu0nKN+FOA54Eat2exomOhMz3g52vTZ0SeMJkBgXX7mPF iqtq+z0bBSDsok9s8Cy3hdOzt8wG/k3SEMhmP49prGO3uuY5OhRRP5jnoEeIudQySO+f xoy4OuYJllx6LCSl9zpAytA7iK1Zgab2+W7BUBqY5eHebDEuRzV4KQAS8uO72JEYO672 pySQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :ironport-sdr:ironport-sdr; bh=xdfni04i/g3p/uUA+h6xJCLZo5GwGDLM1nWFXTKIINw=; b=ijy7eMWjPE/OJ2WqmEmWesLaa2FdaI5Bz8C0bNhRKNa3g9sReCtN55x0NS1ZvUyYcn 7GvruhgTOlkV+g/zlLqOUZFjhTH2fwIOjFBemYiptMEb0LYSBR9qZdqPA4A1E9AZm3Qy aRo8QkLNRvPy5XRI+jWZnaRtuusokLcBaJVsl/1VZkt7w/7O7jzZ3t8hHXU/lF7zhh7p HXFSepXhZzYS56VVkwPiylZHoI/kPEP5OXndHgxnBd4gaUhO2AWrYmMDJU21d2ClHIOZ VbavVU+BSdwErDyXS+FtVWhO3n5cqHKzPLLdgqgJ1Kblo3vZ9L4kzJ6yeh+6uh18zsIM 5e9g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k26si4752932edq.512.2020.06.13.01.15.42; Sat, 13 Jun 2020 01:16:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726475AbgFMILL (ORCPT + 99 others); Sat, 13 Jun 2020 04:11:11 -0400 Received: from mga06.intel.com ([134.134.136.31]:50458 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726451AbgFMILH (ORCPT ); Sat, 13 Jun 2020 04:11:07 -0400 IronPort-SDR: yGPZ1Z7M8oabm0aXoy6aGGKQ/+6/sSPe/D74sp0BcJ56FmQJbC1CnxNH4fQnnVFcERa9AGfi3z HfbAxgCi6MWg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2020 01:11:03 -0700 IronPort-SDR: fM8V1pKNSOdeOzjezraxISaiMrF/G1Qs6okKN6PURfaF5grCqmvCOyouy5RjcG/U1dl+ECKQj+ IT2yY/R8U0lg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,506,1583222400"; d="scan'208";a="474467309" Received: from sqa-gate.sh.intel.com (HELO clx-ap-likexu.tsp.org) ([10.239.48.212]) by fmsmga006.fm.intel.com with ESMTP; 13 Jun 2020 01:10:57 -0700 From: Like Xu To: Paolo Bonzini Cc: Peter Zijlstra , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , ak@linux.intel.com, wei.w.wang@intel.com, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH v12 01/11] perf/x86: Fix variable types for LBR registers Date: Sat, 13 Jun 2020 16:09:46 +0800 Message-Id: <20200613080958.132489-2-like.xu@linux.intel.com> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200613080958.132489-1-like.xu@linux.intel.com> References: <20200613080958.132489-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wei Wang The MSR variable type can be 'unsigned int', which uses less memory than the longer 'unsigned long'. Fix 'struct x86_pmu' for that. The lbr_nr won't be a negative number, so make it 'unsigned int' as well. Suggested-by: Peter Zijlstra (Intel) Signed-off-by: Wei Wang --- arch/x86/events/perf_event.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index e17a3d8a47ed..eb37f6c43c96 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -673,8 +673,8 @@ struct x86_pmu { /* * Intel LBR */ - unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ - int lbr_nr; /* hardware stack size */ + unsigned int lbr_tos, lbr_from, lbr_to, + lbr_nr; /* LBR base regs and size */ u64 lbr_sel_mask; /* LBR_SELECT valid bits */ const int *lbr_sel_map; /* lbr_select mappings */ bool lbr_double_abort; /* duplicated lbr aborts */ -- 2.21.3