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[23.128.96.18]) by mx.google.com with ESMTP id f17si8040157edr.515.2020.06.15.03.08.27; Mon, 15 Jun 2020 03:08:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=P0cRrsg3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729415AbgFOKGe (ORCPT + 99 others); Mon, 15 Jun 2020 06:06:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728773AbgFOKGe (ORCPT ); Mon, 15 Jun 2020 06:06:34 -0400 Received: from mail-il1-x142.google.com (mail-il1-x142.google.com [IPv6:2607:f8b0:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05BE4C061A0E; Mon, 15 Jun 2020 03:06:34 -0700 (PDT) Received: by mail-il1-x142.google.com with SMTP id j19so10546585ilk.9; Mon, 15 Jun 2020 03:06:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=V4ilhIOGf08PxKYEnKjQV/fXI0rSU5dBatEgVzDPnAc=; b=P0cRrsg3JH6SfJ4oLMqbykTLO/eOgi7Euj53OY7iTtxCNRxChA79rSj5NkQ2Edupqx N7INsfzKBCOM3rgdAyGAIDdyshNxznnV8Xz3osw7SQF6gmzqOFC5uX9LoirJnCP6U6JC O2AjzpCtuTlytgLZXF5kTpv3q+9IF2SrQFdsuMDSPP6G6GaDAaR7Jog8iCmO0u6hXKwp Y1S4ZPY0aDWg/GcIFKpoe65TJRjHAvoSf2rduaUbd1v7PpynsqSrwAhMOGcl95m0oV+B tgZwVsAsOQmTp2hnW18vdQXnCZ+ecuBp9aBzFXlJLNH7OG4L8xZkidwnaQBikC6pkoob Q9FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=V4ilhIOGf08PxKYEnKjQV/fXI0rSU5dBatEgVzDPnAc=; b=EmJUct1JyPPIUVWtm6KTjPpy5k8eUmqmq15ibI4/xJ7/AzNFjeTGx9MVYvrroGMDYw h3gCMzSUUPbfAOqmjb/b6dQGdFUZlMr88fLWY8MLI1T6D7PQeDQchN+HX6CGe/kQuF9d D8LduT5pWKYZ73uEBbuXWisfSIcT2IMYZ+ZN3wEDN68O6VgoEj1cUVHZ1RLRHCEYuVSn DabUKfFH0I1N2/fZsn1rKao90OQMHHQkFtSNkz6XQj+iGujz3GGa0YzhDD0j3uK7LmkI DhdUh9jgHXchLPCjmt1+3ecX0s7lo0oGkl15nZkIbBFfzgLDDx+qgpJxEqkjgybkq3zY U9Jg== X-Gm-Message-State: AOAM533ybE/JB3hMGfX06ZXrOF2vcxwukBUTQYvHJ1ZpSlGZ/a6Rthko nER3loQSAsLze733TsbRxhvU3n82/4T5G4NH/6I= X-Received: by 2002:a92:5bd2:: with SMTP id c79mr23408564ilg.218.1592215593037; Mon, 15 Jun 2020 03:06:33 -0700 (PDT) MIME-Version: 1.0 References: <1590564453-24499-1-git-send-email-dillon.minfei@gmail.com> <1590564453-24499-3-git-send-email-dillon.minfei@gmail.com> <2273a168-7b14-9e28-5904-b9d2c2e2d9d3@st.com> In-Reply-To: <2273a168-7b14-9e28-5904-b9d2c2e2d9d3@st.com> From: dillon min Date: Mon, 15 Jun 2020 18:05:56 +0800 Message-ID: Subject: Re: [PATCH v6 2/9] ARM: dts: stm32: Add pin map for ltdc & spi5 on stm32f429-disco board To: Alexandre Torgue Cc: Rob Herring , p.zabel@pengutronix.de, Maxime Coquelin , thierry.reding@gmail.com, Sam Ravnborg , Dave Airlie , Daniel Vetter , Michael Turquette , Stephen Boyd , Andy Shevchenko , =?UTF-8?Q?Noralf_Tr=C3=B8nnes?= , Linus Walleij , Mark Brown , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux ARM , Linux Kernel Mailing List , linux-spi , linux-stm32@st-md-mailman.stormreply.com, "open list:DRM PANEL DRIVERS" , linux-clk , Hua Dillon Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jun 15, 2020 at 5:45 PM Alexandre Torgue wrote: > > Hi Dillon > > On 5/27/20 9:27 AM, dillon.minfei@gmail.com wrote: > > From: dillon min > > > > This patch adds the pin configuration for ltdc and spi5 controller > > on stm32f429-disco board. > > > > Signed-off-by: dillon min > > --- > > arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 67 ++++++++++++++++++++++++++++++++++ > > 1 file changed, 67 insertions(+) > > > > diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi > > index 392fa143ce07..0eb107f968cd 100644 > > --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi > > +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi > > @@ -316,6 +316,73 @@ > > }; > > }; > > > > + ltdc_pins_f429_disco: ltdc-1 { > > Sorry I missed this issue during review. I changed ltdc_pins_f429_disco > by ltdc_pins_b when I applied your patch. Okay, thanks for reviewing. Regrades, Dillon, > > > Regards > alex > > > + pins { > > + pinmux = , > > + /* LCD_HSYNC */ > > + , > > + /* LCD_VSYNC */ > > + , > > + /* LCD_CLK */ > > + , > > + /* LCD_R2 */ > > + , > > + /* LCD_R3 */ > > + , > > + /* LCD_R4 */ > > + , > > + /* LCD_R5 */ > > + , > > + /* LCD_R6*/ > > + , > > + /* LCD_R7 */ > > + , > > + /* LCD_G2 */ > > + , > > + /* LCD_G3 */ > > + , > > + /* LCD_G4 */ > > + , > > + /* LCD_B2 */ > > + , > > + /* LCD_B3*/ > > + , > > + /* LCD_G5 */ > > + , > > + /* LCD_G6 */ > > + , > > + /* LCD_G7 */ > > + , > > + /* LCD_B4 */ > > + , > > + /* LCD_B5 */ > > + , > > + /* LCD_B6 */ > > + , > > + /* LCD_B7 */ > > + ; > > + /* LCD_DE */ > > + slew-rate = <2>; > > + }; > > + }; > > + > > + spi5_pins: spi5-0 { > > + pins1 { > > + pinmux = , > > + /* SPI5_CLK */ > > + ; > > + /* SPI5_MOSI */ > > + bias-disable; > > + drive-push-pull; > > + slew-rate = <0>; > > + }; > > + pins2 { > > + pinmux = ; > > + /* SPI5_MISO */ > > + bias-disable; > > + }; > > + }; > > + > > dcmi_pins: dcmi-0 { > > pins { > > pinmux = , /* DCMI_HSYNC */ > >