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From:   Georgi Djakov <georgi.djakov@linaro.org>
To:     svarbanov@mm-sol.com
Cc:     bjorn.andersson@linaro.org, vkoul@kernel.org, sanm@codeaurora.org,
        mgautam@codeaurora.org, agross@kernel.org, bhelgaas@google.com,
        robh@kernel.org, lorenzo.pieralisi@arm.com,
        linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Georgi Djakov <georgi.djakov@linaro.org>
Subject: [PATCH] PCI: qcom: Disable power management for uPD720201 USB3 controller
Date:   Mon, 15 Jun 2020 21:24:13 +0300
Message-Id: <20200615182413.15649-1-georgi.djakov@linaro.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

The uPD720201 USB3 host controller (connected to PCIe) on the Dragonboard
845c is often failing during suspend and resume. The following messages
are seen over the console:

  PM: suspend entry (s2idle)
  Filesystems sync: 0.000 seconds
  Freezing user space processes ... (elapsed 0.001 seconds) done.
  OOM killer disabled.
  Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
  printk: Suspending console(s) (use no_console_suspend to debug)
  dwc3-qcom a8f8800.usb: HS-PHY not in L2
  dwc3-qcom a6f8800.usb: HS-PHY not in L2
  xhci_hcd 0000:01:00.0: can't change power state from D3hot to D0 (config
  space inaccessible)
  xhci_hcd 0000:01:00.0: can't change power state from D3hot to D0 (config
  space inaccessible)
  xhci_hcd 0000:01:00.0: Controller not ready at resume -19
  xhci_hcd 0000:01:00.0: PCI post-resume error -19!
  xhci_hcd 0000:01:00.0: HC died; cleaning up

Then the USB devices are not functional anymore. Let's disable the PM of
the controller for now, as this will at least keep USB devices working
even after suspend and resume.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 138e1a2d21cc..c1f502682a19 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1439,6 +1439,13 @@ static void qcom_fixup_class(struct pci_dev *dev)
 {
 	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
 }
+
+static void qcom_fixup_nopm(struct pci_dev *dev)
+{
+	dev->pm_cap = 0;
+	dev_info(&dev->dev, "Disabling PCI power management\n");
+}
+
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class);
@@ -1446,6 +1453,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RENESAS, 0x0014, qcom_fixup_nopm);
 
 static struct platform_driver qcom_pcie_driver = {
 	.probe = qcom_pcie_probe,