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Date:   Tue, 16 Jun 2020 01:20:42 -0700
From:   Sean Christopherson <sean.j.christopherson@intel.com>
To:     Xiaoyao Li <xiaoyao.li@intel.com>
Cc:     Paolo Bonzini <pbonzini@redhat.com>,
        Vitaly Kuznetsov <vkuznets@redhat.com>,
        Jim Mattson <jmattson@google.com>, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] KVM: X86: Fix MSR range of APIC registers in X2APIC mode
Message-ID: <20200616082042.GE26491@linux.intel.com>
References: <20200616073307.16440-1-xiaoyao.li@intel.com>
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On Tue, Jun 16, 2020 at 03:33:07PM +0800, Xiaoyao Li wrote:
> Only MSR address range 0x800 through 0x8ff is architecturally reserved
> and dedicated for accessing APIC registers in x2APIC mode.
> 
> Fixes: 0105d1a52640 ("KVM: x2apic interface to lapic")
> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---

And perhaps more importantly, there are real MSRs that are overlapped,
e.g. MSR_IA32_TME_ACTIVATE.  This probably warrants a Cc to stable; as you
found out the hard way, this breaks ignore_msrs.

Reviewed-by: Sean Christopherson <sean.j.christopherson@intel.com>