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From:   Yash Shah <yash.shah@sifive.com>
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        Yash Shah <yash.shah@sifive.com>
Subject: [PATCH 2/3] riscv: dts: fu540-c000: define hart clocks
Date:   Tue, 16 Jun 2020 17:31:03 +0530
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Declare that each hart defined in the FU540 DT data is clocked by the
COREPLL. This is in preparation for enabling CPUFreq for the
FU540-C000 SoC on the HiFive Unleashed board.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 7db8610..735e102 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -30,6 +30,7 @@
 			i-cache-size = <16384>;
 			reg = <0>;
 			riscv,isa = "rv64imac";
+			clocks = <&prci PRCI_CLK_COREPLL>;
 			status = "disabled";
 			cpu0_intc: interrupt-controller {
 				#interrupt-cells = <1>;
@@ -55,6 +56,7 @@
 			riscv,isa = "rv64imafdc";
 			tlb-split;
 			next-level-cache = <&l2cache>;
+			clocks = <&prci PRCI_CLK_COREPLL>;
 			cpu1_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -79,6 +81,7 @@
 			riscv,isa = "rv64imafdc";
 			tlb-split;
 			next-level-cache = <&l2cache>;
+			clocks = <&prci PRCI_CLK_COREPLL>;
 			cpu2_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -103,6 +106,7 @@
 			riscv,isa = "rv64imafdc";
 			tlb-split;
 			next-level-cache = <&l2cache>;
+			clocks = <&prci PRCI_CLK_COREPLL>;
 			cpu3_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -127,6 +131,7 @@
 			riscv,isa = "rv64imafdc";
 			tlb-split;
 			next-level-cache = <&l2cache>;
+			clocks = <&prci PRCI_CLK_COREPLL>;
 			cpu4_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
-- 
2.7.4