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([2601:646:c200:1ef2:2854:eba6:e44d:d731]) by smtp.gmail.com with ESMTPSA id d6sm3470492pjh.5.2020.06.16.14.17.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Jun 2020 14:17:18 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable From: Andy Lutomirski Mime-Version: 1.0 (1.0) Subject: Re: [PATCH] x86/fpu: Reset MXCSR to default in kernel_fpu_begin() Date: Tue, 16 Jun 2020 14:17:16 -0700 Message-Id: <1D569B6B-B8C3-497E-8A74-2E1A3D46299E@amacapital.net> References: <20200616180123.GL13515@zn.tnic> Cc: x86-ml , jpa@kernelbug.mail.kapsi.fi, Dave Hansen , "H. Peter Anvin" , Sebastian Andrzej Siewior , lkml In-Reply-To: <20200616180123.GL13515@zn.tnic> To: Borislav Petkov X-Mailer: iPhone Mail (17F80) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Jun 16, 2020, at 11:01 AM, Borislav Petkov wrote: >=20 > =EF=BB=BFOn Tue, Jun 16, 2020 at 09:53:39AM -0700, Andy Lutomirski wrote: >>> On Tue, Jun 16, 2020 at 2:53 AM Borislav Petkov wrote: >>>=20 >>> Ok, >>>=20 >>> here's the fix first so that it goes in. I'll hammer on the test case la= ter. >>=20 >> Does the 32-bit case need FNINIT? >=20 > Pasting from IRC: >=20 > I'm thinking if you'd need to reinit the FPU, then you need to do it for > both, not only 32-bit or do you mean something else? Also, if you end up > doing FNSAVE (old CPU) that one reinits state. We definitely need to sanitize MXCSR for kernel fpu if kernel fpu means SSE2= . If kernel fpu means x87, we need to fix the fpu control word. On x86_64, I suspect the UEFI ABI technically requires a clean x87 control w= ord too. If we=E2=80=99re willing to declare that the kernel proper won=E2=80= =99t use x87, then we could shove that into the UEFI code. >=20 > Whatever we decide doing, this should be a separate patch anyway. >=20 > Thx. >=20 > --=20 > Regards/Gruss, > Boris. >=20 > https://people.kernel.org/tglx/notes-about-netiquette