Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp127270ybt; Tue, 16 Jun 2020 18:45:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwB3ktO0DAujthjSUk1ro0ox8TOB7i8y0RA0CRMVTv2K0fkwVwU/ibqyizEnLYo+y/paXfv X-Received: by 2002:a17:906:2e50:: with SMTP id r16mr5216855eji.305.1592358351245; Tue, 16 Jun 2020 18:45:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592358351; cv=none; d=google.com; s=arc-20160816; b=A1/Q4YZMiw4RJ99UOgfAVFSG/GstXRobShpMzc0Sn5rpby7c0OsLIlskyRQ8EsWFau b53YzYJuzhhxV5y2T4lbhy55+yT2MkHt9CdL9Aiux3pGVhuLQspPnxcbilzEKgmmmELL GUf/zy06dZuoewBY9m4Nstvng2gbq0nthjFncNu8dDCmYyLnroExhr+dbYwETuKtqd2t SxHkTQkoHvaTLlVgjC/zuxSzTqBdmKa0bJUKv5nyq4Zvgo7viJw3TUBCYJtT7iTmKON2 gmEUtT7OfU3pTDdhbKzss8IuVO6MitnR5xTmVp2gPQZQToZWePb6RP4T8RX8efc7WOom 59Qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=yGbs5SDi4Dd0+0xT6nDOtBMbjmUT+S0MvKYM2ZVqVhs=; b=G8aYR4FkVShdQ+yNO4QzhD47oYzKaMKp8/y2QBuFa6rQpy6akU8pgKSNidNkbFf+Au 8/D1P/G1ryRE2OUdELorGs5ACgwSIrc9mSHO+y+KLG1bZKx0QVrr6l5Ld+oUmfyeVMMI 1nUYaWcqqd0vieftNz6aPasM1w+UmQuvdvzJQ9638yz9cq6G2T6+b7Nqh1qzRpB64zag RxRJyCafoleGLKMmq0XgQkmD7tmYedcotaLj+7/Jqe1aJSHWFp96i9FHMOmA0FSscnp+ 7TKEiVHazigVm2rnQ5vmZs9DI1GIhhUor/a9dhcZjV5hhZEkLq3GOCwV6AGr2SwllenH jG8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=OKXaPg8a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id l26si12757756ejc.496.2020.06.16.18.45.27; Tue, 16 Jun 2020 18:45:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=OKXaPg8a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727001AbgFQBlH (ORCPT + 99 others); Tue, 16 Jun 2020 21:41:07 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:19574 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726736AbgFQBjl (ORCPT ); Tue, 16 Jun 2020 21:39:41 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 16 Jun 2020 18:38:01 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 16 Jun 2020 18:39:40 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 16 Jun 2020 18:39:40 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 17 Jun 2020 01:39:39 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 17 Jun 2020 01:39:39 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.186]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 16 Jun 2020 18:39:38 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v2 10/18] dt-bindings: tegra: Update VI and CSI bindings with port info Date: Tue, 16 Jun 2020 18:41:26 -0700 Message-ID: <1592358094-23459-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> References: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1592357881; bh=yGbs5SDi4Dd0+0xT6nDOtBMbjmUT+S0MvKYM2ZVqVhs=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=OKXaPg8adLk/991hSEryvnuKB/ne6JxrIM8At9YhEYriNsqBOAUJLebYrZEAQWVcb eesjBi5UetzsFovSsB5aqbf+uMklTkg+Zhf3YH40aX9qGhYLZVoRrrfVendZYGp2dX lHzh/p32RnFpL8mnxeH5K73PW6le1eXPSGi1mnNZ11JfbT08kftc40H9FjTcC9OKdN ht6A5DgyY/DLCGAwYDE5mPWB1kAnCRMxOlR50ixBiZtmKM/dWlt19AUq+yJczW5U61 TOBJLivEmAvib5yvDf4DoYppvU9YdVlYeNBnIiexBZ6hYhBMpttQ6/bPTMTf3oNX9Q VmOUwRpRg6DHw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update VI and CSI bindings to add port and endpoint nodes as per media video-interfaces DT binding document. Signed-off-by: Sowjanya Komatineni --- .../display/tegra/nvidia,tegra20-host1x.txt | 92 +++++++++++++++++++++- 1 file changed, 90 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 4731921..ac63ae4a 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -51,8 +51,16 @@ of the following host1x client modules: - vi - Tegra210: - power-domains: Must include venc powergate node as vi is in VE partition. - - Tegra210 has CSI part of VI sharing same host interface and register space. - So, VI device node should have CSI child node. + + ports (optional node) + vi can have optional ports node and max 6 ports are supported. Each port + should have single 'endpoint' child node. All port nodes are grouped under + ports node. Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt + + csi (required node) + Tegra210 has CSI part of VI sharing same host interface and register space. + So, VI device node should have CSI child node. - csi: mipi csi interface to vi @@ -65,6 +73,46 @@ of the following host1x client modules: - power-domains: Must include sor powergate node as csicil is in SOR partition. + channel (optional nodes) + Maximum 6 channels are supported with each csi brick as either x4 or x2 + based on hw connectivity to sensor. + + Required properties: + - reg: csi port number. Valid port numbers are 0 through 5. + - nvidia,mipi-calibrate: Should contain a phandle and a specifier + specifying which pads are used by this CSI port and need to be + calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt. + + Each channel node must contain 2 port nodes which can be grouped + under 'ports' node and each port should have a single child 'endpoint' + node. + + ports node + Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt + + ports node must contain below 2 port nodes. + port@0 with single child 'endpoint' node always a sink. + port@1 with single child 'endpoint' node always a source. + + port@0 (required node) + Required properties: + - reg: 0 + + endpoint (required node) + Required properties: + - data-lanes: an array of data lane from 1 to 4. Valid array + lengths are 1/2/4. + - remote-endpoint: phandle to sensor 'endpoint' node. + + port@1 (required node) + Required properties: + - reg: 1 + + endpoint (required node) + Required properties: + - remote-endpoint: phandle to vi port 'endpoint' node. + - epp: encoder pre-processor Required properties: @@ -340,6 +388,18 @@ Example: ranges = <0x0 0x0 0x54080000 0x2000>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + imx219_vi_in0: endpoint { + remote-endpoint = <&imx219_csi_out0>; + }; + }; + }; + csi@838 { compatible = "nvidia,tegra210-csi"; reg = <0x838 0x1300>; @@ -362,6 +422,34 @@ Example: <&tegra_car TEGRA210_CLK_CSI_TPG>; clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; power-domains = <&pd_sor>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + nvidia,mipi-calibrate = <&mipi 0x001>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + imx219_csi_in0: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&imx219_out0>; + }; + }; + + port@1 { + reg = <1>; + imx219_csi_out0: endpoint { + remote-endpoint = <&imx219_vi_in0>; + }; + }; + }; + }; }; }; -- 2.7.4