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Subject: Re: [PATCH V7 0/4] Add APSS clock controller support for IPQ6018
To:     agross@kernel.org, bjorn.andersson@linaro.org,
        mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
        linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
References: <1591440907-20021-1-git-send-email-sivaprak@codeaurora.org>
From:   Sivaprakash Murugesan <sivaprak@codeaurora.org>
Message-ID: <852c7804-b1b3-2d78-00f6-b67b9fd4e720@codeaurora.org>
Date:   Thu, 18 Jun 2020 12:30:58 +0530
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Ping!

Hi Stephen,

Is it possible for you to review this series? We have regulators and few 
other patches

depend on this patch, it would be great if you could provide your inputs 
on this.

Thanks,

Siva

On 6/6/2020 4:25 PM, Sivaprakash Murugesan wrote:
> The CPU on Qualcomm's IPQ6018 devices are primarily fed by APSS PLL and XO,
> these are connected to a clock mux and enable block.
>
> This patch series adds support for these clocks and inturn enables clocks
> required for CPU freq.
>
> [V7]
>   * Removed dts patch from this series, will send that separately
>   * Addressed Rob's minor comment on the binding
>   * Patch 1 depends on a53 pll bindings
>     https://lkml.org/lkml/2020/5/4/60
> [V6]
>   * Split mailbox driver from this series, mailbox changes will sent as a
>     separate series
>   * Addressed review comments from Stephen
> [V5]
>   * Addressed Bjorn comments on apss clk and dt-bindings
>   * Patch 2 depends on a53 pll dt-bindings
>     https://www.spinics.net/lists/linux-clk/msg48358.html
> [V4]
>   * Re-written PLL found on IPQ platforms as a separate driver
>   * Addressed stephen's comments on apss clock controller and pll
>   * Addressed Rob's review comments on bindings
>   * moved a53 pll binding from this series as it is not applicable, will send
>     it separately.
> [V3]
>   * Fixed dt binding check error in patch2
>     dt-bindings: clock: Add YAML schemas for QCOM A53 PLL
> [V2]
>   * Restructred the patch series as there are two different HW blocks,
>     the mux and enable belongs to the apcs block and PLL has a separate HW
>     block.
>   * Converted qcom mailbox and qcom a53 pll documentation to yaml.
>   * Addressed review comments from Stephen, Rob and Sibi where it is applicable.
>   * Changed this cover letter to state the purpose of this patch series
>
> Sivaprakash Murugesan (4):
>    dt-bindings: clock: add ipq6018 a53 pll compatible
>    clk: qcom: Add ipq apss pll driver
>    clk: qcom: Add DT bindings for ipq6018 apss clock controller
>    clk: qcom: Add ipq6018 apss clock controller
>
>   .../devicetree/bindings/clock/qcom,a53pll.yaml     |  18 ++++
>   drivers/clk/qcom/Kconfig                           |  19 ++++
>   drivers/clk/qcom/Makefile                          |   2 +
>   drivers/clk/qcom/apss-ipq-pll.c                    |  95 ++++++++++++++++++
>   drivers/clk/qcom/apss-ipq6018.c                    | 106 +++++++++++++++++++++
>   include/dt-bindings/clock/qcom,apss-ipq.h          |  12 +++
>   6 files changed, 252 insertions(+)
>   create mode 100644 drivers/clk/qcom/apss-ipq-pll.c
>   create mode 100644 drivers/clk/qcom/apss-ipq6018.c
>   create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h
>