Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp1375334ybt; Thu, 18 Jun 2020 07:19:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyBOLjzJzP96OB0f0CFRcfg3/5CatGjrS0F24wsBnLErLSz8+Y/qjVyTLSs/WD0jGxJTkPe X-Received: by 2002:a17:906:3da:: with SMTP id c26mr3952621eja.451.1592489974398; Thu, 18 Jun 2020 07:19:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592489974; cv=none; d=google.com; s=arc-20160816; b=r0T+4U1rkT/tjDY6YfqPXVuDPS0OaWRpdtI0kG0DRs5d1i6P/G5qWpfcTPj4aLiK3X G9Lc9KC4nwNpLsUu9t9lolv6CKgPEBWi/KFfseAq2lgWhTh5CXOYFTttmiT5/keOc2Nf xGKPKauRNYYqpoSkvfVQi7EUqmOrbAwriSr00SkJdBZaTebLL852a1Igf2cYrw0ly7AU MG2S4FbVz0IbT1Z5LeWVQnCd5AHkgMRYTYZIKGbmPPzz50SH1wbWBqEZlQlUgdbPa7Mh x+hSzjzb+KK2+skEqGioKGBKLQnWmgV8nKTBi8ZqX7DiSbRTecKSw3uYt770HuHC3/Ba b4wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :ironport-sdr:dkim-signature; bh=zayOy/JpZl9FmNF00SPt0qFmjnM336MxWPUIE722FTM=; b=bg5JVSn54yUt/EO1KMYrBbUN6M1711evj4PBaxgI4vsbEViFN5WulOJNh8YqNTOdER lMOHiggyhH9ALIY8WNSTm697aoXkZpvRCNw7+WWKyiU9Og5iMfj8CNoEgWkVWlPFD2J8 /l3Tjm2Ld2MMk+mDVkibzIunBXO9QATKzblxJooQ2i+BqZ5hIIAtkhBIqEzEAWAdjSpH zeUHUfSIAkHPQ/+uVCWzBPcCNOItd96Y0A6KwrNSjMDE+V/AQnDWctTkd3WcYzM33JO8 vJ/mVeMUAMasZ9w2rti4qk+lCRixHA3IpxTs1BWgihU90iJ/ORT7a1Hv0WCNQ+1Iy/ul 4Pyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@microchip.com header.s=mchp header.b=1lXZQiVc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t18si2261123edt.132.2020.06.18.07.19.10; Thu, 18 Jun 2020 07:19:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=fail header.i=@microchip.com header.s=mchp header.b=1lXZQiVc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730770AbgFROOK (ORCPT + 99 others); Thu, 18 Jun 2020 10:14:10 -0400 Received: from esa2.microchip.iphmx.com ([68.232.149.84]:53787 "EHLO esa2.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730714AbgFROOB (ORCPT ); Thu, 18 Jun 2020 10:14:01 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1592489641; x=1624025641; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xXlRuWDsgHzsC/cK9WaU+YzlpcD2wIPLoPF5OvjRa5Y=; b=1lXZQiVcFSXh5bdX45jELHOgbzvduRNu4pmQiC7sohksO67miodsiHlF UqSpCA0LkhTuk4ojE4Zw2HDEdpvWy+LVP1v5f0IYu8VB1xvAqaCylzJXG yzmcgjblYJUKo6FLUjFnnlrrCLLiSfj2QJoVCYoPuO7sTGJzWEUjIwn93 aDVYRJY+zrz6M0eKnWuIYGvys3uZd8aHYy5hnrT1IZIEusRFNV5MRdHoG 54Y2wapRtyS1ndRUsIhMyN9eaD8RR1sAwM9XC0+hwyrpkeMvdk5SH3hn1 CKXykcNj5SJNV7uLKN4fOIxltMCJm4yQoe+l3olrDDw4Gl8yrtzXSdNmQ w==; IronPort-SDR: 35EFXpDv5rWakdQUkUCRxWM0ZzuOx/gfmCp8J5dvbSiaJVvcaUDiePTZzz7EKzfJh3P3+l7+1c 08B/l+nSGHojSCwVCtPwoBAY6U6kkdEdGJvAPpj1rgjsLmOlwbNGxRd1IFWOrn/Wg9sb15YQ1K Lo6j14ILgBTdNeAmoivvQ0MDuhUhTpvrQvCT53gwGPLF5cpIcMCGeHWCCx6zhLk1KVMuCpd4jM /aU+1QMhH1ZXjAsfP0IO5+a781yk7yQNpX+z16el6OUcvI051iKWaYKhpeF1thtvFvIXnLoXRO xL0= X-IronPort-AV: E=Sophos;i="5.73,526,1583218800"; d="scan'208";a="78953903" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 18 Jun 2020 07:14:00 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 18 Jun 2020 07:13:53 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 18 Jun 2020 07:13:51 -0700 From: Lars Povlsen To: Ulf Hansson , Adrian Hunter , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH v4 3/3] arm64: dts: sparx5: Add Sparx5 eMMC support Date: Thu, 18 Jun 2020 16:13:26 +0200 Message-ID: <20200618141326.25723-4-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200618141326.25723-1-lars.povlsen@microchip.com> References: <20200618141326.25723-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds eMMC support to the applicable Sparx5 board configuration files. Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 24 +++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 23 ++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb134_emmc.dts | 23 ++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb135_emmc.dts | 23 ++++++++++++++++++ 4 files changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 84bca999420ef..c9dbd1a8b22b6 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { compatible = "microchip,sparx5"; @@ -162,6 +163,20 @@ timer1: timer@600105000 { interrupts = ; }; + sdhci0: sdhci@600800000 { + compatible = "microchip,dw-sparx5-sdhci"; + status = "disabled"; + reg = <0x6 0x00800000 0x1000>; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + clocks = <&clks CLK_ID_AUX1>; + clock-names = "core"; + assigned-clocks = <&clks CLK_ID_AUX1>; + assigned-clock-rates = <800000000>; + interrupts = ; + bus-width = <8>; + }; + gpio: pinctrl@6110101e0 { compatible = "microchip,sparx5-pinctrl"; reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; @@ -191,6 +206,15 @@ i2c2_pins: i2c2-pins { pins = "GPIO_28", "GPIO_29"; function = "twi2"; }; + + emmc_pins: emmc-pins { + pins = "GPIO_34", "GPIO_35", "GPIO_36", + "GPIO_37", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + function = "emmc"; + }; }; i2c0: i2c@600101000 { diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 91ee5b6cfc37a..573309fe45823 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -16,6 +16,29 @@ memory@0 { }; }; +&gpio { + emmc_pins: emmc-pins { + /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" + * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) + */ + pins = "GPIO_34", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + drive-strength = <3>; + function = "emmc"; + }; +}; + +&sdhci0 { + status = "okay"; + bus-width = <8>; + non-removable; + pinctrl-0 = <&emmc_pins>; + max-frequency = <8000000>; + microchip,clock-delay = <10>; +}; + &i2c1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts index 10081a66961bb..bbb9852c1f151 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts @@ -15,3 +15,26 @@ memory@0 { reg = <0x00000000 0x00000000 0x10000000>; }; }; + +&gpio { + emmc_pins: emmc-pins { + /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" + * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) + */ + pins = "GPIO_34", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + drive-strength = <3>; + function = "emmc"; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + non-removable; + max-frequency = <52000000>; + bus-width = <8>; + microchip,clock-delay = <10>; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts index 741f0e12260e5..f82266fe2ad49 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts @@ -15,3 +15,26 @@ memory@0 { reg = <0x00000000 0x00000000 0x10000000>; }; }; + +&gpio { + emmc_pins: emmc-pins { + /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" + * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) + */ + pins = "GPIO_34", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + drive-strength = <3>; + function = "emmc"; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + non-removable; + max-frequency = <52000000>; + bus-width = <8>; + microchip,clock-delay = <10>; +}; -- 2.27.0