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Subject: Re: [PATCH v6 6/7] clk: mediatek: add UART0 clock support
To:     Hanks Chen <hanks.chen@mediatek.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Sean Wang <sean.wang@kernel.org>
Cc:     mtk01761 <wendell.lin@mediatek.com>,
        Andy Teng <andy.teng@mediatek.com>, linux-gpio@vger.kernel.org,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-clk@vger.kernel.org, wsd_upstream@mediatek.com,
        CC Hwang <cc.hwang@mediatek.com>,
        Loda Chou <loda.chou@mediatek.com>
References: <1592480018-3340-1-git-send-email-hanks.chen@mediatek.com>
 <1592480018-3340-7-git-send-email-hanks.chen@mediatek.com>
From:   Matthias Brugger <matthias.bgg@gmail.com>
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Message-ID: <a61ed70c-a360-f3af-e215-6377ea25a6ab@gmail.com>
Date:   Thu, 18 Jun 2020 17:51:18 +0200
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On 18/06/2020 13:33, Hanks Chen wrote:
> Add MT6779 UART0 clock support.
> 

Please a dd fixes tag:

Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")

> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
> Signed-off-by: mtk01761 <wendell.lin@mediatek.com>

Must be a real name not "mtk01761"

> ---
>  drivers/clk/mediatek/clk-mt6779.c |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
> index 9766ccc..6e0d3a1 100644
> --- a/drivers/clk/mediatek/clk-mt6779.c
> +++ b/drivers/clk/mediatek/clk-mt6779.c
> @@ -919,6 +919,8 @@
>  		    "pwm_sel", 19),
>  	GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
>  		    "pwm_sel", 21),
> +	GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> +		    "uart_sel", 22),
>  	GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
>  		    "uart_sel", 23),
>  	GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
>