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Date:   Thu, 18 Jun 2020 20:04:15 +0300
From:   Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To:     Shiju Jose <shiju.jose@huawei.com>
Cc:     "linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "rjw@rjwysocki.net" <rjw@rjwysocki.net>,
        "helgaas@kernel.org" <helgaas@kernel.org>,
        "bp@alien8.de" <bp@alien8.de>,
        "james.morse@arm.com" <james.morse@arm.com>,
        "lenb@kernel.org" <lenb@kernel.org>,
        "tony.luck@intel.com" <tony.luck@intel.com>,
        "dan.carpenter@oracle.com" <dan.carpenter@oracle.com>,
        "zhangliguang@linux.alibaba.com" <zhangliguang@linux.alibaba.com>,
        "Wangkefeng (OS Kernel Lab)" <wangkefeng.wang@huawei.com>,
        "jroedel@suse.de" <jroedel@suse.de>,
        Linuxarm <linuxarm@huawei.com>,
        yangyicong <yangyicong@huawei.com>,
        Jonathan Cameron <jonathan.cameron@huawei.com>,
        tanxiaofei <tanxiaofei@huawei.com>
Subject: Re: [PATCH v10 2/2] PCI: hip: Add handling of HiSilicon HIP PCIe
 controller errors
Message-ID: <20200618170415.GY2428291@smile.fi.intel.com>
References: <20200618154051.639-3-shiju.jose@huawei.com>
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On Thu, Jun 18, 2020 at 04:35:31PM +0000, Shiju Jose wrote:
> >-----Original Message-----
> >From: Andy Shevchenko [mailto:andriy.shevchenko@linux.intel.com]
> >Sent: 18 June 2020 16:56
> >To: Shiju Jose <shiju.jose@huawei.com>
> >Cc: linux-acpi@vger.kernel.org; linux-pci@vger.kernel.org; linux-
> >kernel@vger.kernel.org; rjw@rjwysocki.net; helgaas@kernel.org;
> >bp@alien8.de; james.morse@arm.com; lenb@kernel.org;
> >tony.luck@intel.com; dan.carpenter@oracle.com;
> >zhangliguang@linux.alibaba.com; Wangkefeng (OS Kernel Lab)
> ><wangkefeng.wang@huawei.com>; jroedel@suse.de; Linuxarm
> ><linuxarm@huawei.com>; yangyicong <yangyicong@huawei.com>; Jonathan
> >Cameron <jonathan.cameron@huawei.com>; tanxiaofei
> ><tanxiaofei@huawei.com>
> >Subject: Re: [PATCH v10 2/2] PCI: hip: Add handling of HiSilicon HIP PCIe
> >controller errors
> >
> >On Thu, Jun 18, 2020 at 04:40:51PM +0100, Shiju Jose wrote:

...

> >> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
> >
> >Hmm... Did I give a tag?

Yes, and please, be sure that you got explicit tags from reviewers.

...

> >> +	for_each_set_bit_from(idx, (const unsigned long *)&edata->val_bits,
> >
> >Can't you make val_bits unsigned long? Because this casting is incorrect.
> >Otherwise, make a local copy into unsigned long variable.
> 
> The data val_bits in the error record is 64 bits, thus used u64.
> Casting is added because of a compilation warning on _find_nex_bit_ function as it 
> expects the type of the address as const unsigned long*.
> Probably I will make local copy of val_bits into unsigned long variable.

I see.  So, something like this:

	unsigned long bits[] = { BITMAP_FROM_U64(edata->val_bits) };
	...
	for_each_set_bit_from(i, bits, ...)
		...

looks plausible. Or if you have better idea...

-- 
With Best Regards,
Andy Shevchenko