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[23.128.96.18]) by mx.google.com with ESMTP id wp10si2307876ejb.56.2020.06.18.11.10.58; Thu, 18 Jun 2020 11:11:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730580AbgFROJ0 (ORCPT + 99 others); Thu, 18 Jun 2020 10:09:26 -0400 Received: from mga09.intel.com ([134.134.136.24]:40597 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728707AbgFROJX (ORCPT ); Thu, 18 Jun 2020 10:09:23 -0400 IronPort-SDR: i6cPF39gFNA01SAd73wbk9u0aOC++47FXGLygCdaxfVYR8GJJqskWT5OTseoRYYxoohEYO3OJw bEN5fpvo+cqg== X-IronPort-AV: E=McAfee;i="6000,8403,9655"; a="144096349" X-IronPort-AV: E=Sophos;i="5.73,526,1583222400"; d="scan'208";a="144096349" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2020 07:09:22 -0700 IronPort-SDR: xOK2I18398q2bmHJzuXqSreeiFdtuKhbyKrvQdbyZ1Vtbwufhq4RsqmJvxkzrdXG+X+63VfnyO DYa2L07P7BKw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,526,1583222400"; d="scan'208";a="277635259" Received: from ryanr2x-mobl1.amr.corp.intel.com (HELO [10.255.0.133]) ([10.255.0.133]) by orsmga006.jf.intel.com with ESMTP; 18 Jun 2020 07:09:15 -0700 Subject: Re: [PATCH 1/4] X86: Update mmu_cr4_features during feature identification To: John Andersen , corbet@lwn.net, pbonzini@redhat.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com, shuah@kernel.org, sean.j.christopherson@intel.com, liran.alon@oracle.com, drjones@redhat.com, rick.p.edgecombe@intel.com, kristen@linux.intel.com Cc: vkuznets@redhat.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, mchehab+huawei@kernel.org, gregkh@linuxfoundation.org, paulmck@kernel.org, pawan.kumar.gupta@linux.intel.com, jgross@suse.com, mike.kravetz@oracle.com, oneukum@suse.com, luto@kernel.org, peterz@infradead.org, fenghua.yu@intel.com, reinette.chatre@intel.com, vineela.tummalapalli@intel.com, dave.hansen@linux.intel.com, arjan@linux.intel.com, caoj.fnst@cn.fujitsu.com, bhe@redhat.com, nivedita@alum.mit.edu, keescook@chromium.org, dan.j.williams@intel.com, eric.auger@redhat.com, aaronlewis@google.com, peterx@redhat.com, makarandsonare@google.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, kernel-hardening@lists.openwall.com References: <20200617190757.27081-1-john.s.andersen@intel.com> <20200617190757.27081-2-john.s.andersen@intel.com> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200617190757.27081-2-john.s.andersen@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Overall this looks pretty good. For all the maintainers on cc, we try to do internal reviews of these before they're submitted. This one got missed, sorry about that. On 6/17/20 12:07 PM, John Andersen wrote: > In identify_cpu when setting up SMEP/SMAP/UMIP call > cr4_set_bits_and_update_boot instead of cr4_set_bits. This ensures that > mmu_cr4_features contains those bits, and does not disable those > protections when in hibernation asm. When I'm writing comments, I try to use parenthesis for functions(), which leaves variable_names plain. I also try not to dive directly into the function names. This description assumes that the reader knows the subtle difference between cr4_set_bits_and_update_boot() and of cr4_set_bits(). A sentence or two of background here can save a reviewer a dive into the source code. > setup_arch updates mmu_cr4_features to save what identified features are > supported for later use in hibernation asm when cr4 needs to be modified > to toggle PGE. cr4 writes happen in restore_image and restore_registers. > setup_arch occurs before identify_cpu, this leads to mmu_cr4_features > not containing some of the cr4 features which were enabled via > identify_cpu when hibernation asm is executed. This fails to address the bigger picture. I assume you end up wanting this because without it hibernation is not compatible with CR pinning. Shouldn't that be mentioned? I also wonder why we even need two classes of cr4_set_bits(). Are there features we *want* to disable before entering the hibernation assembly? For instance, why not leave MCE enabled in there? What about PCIDs or OSPKE? Does it hurt? > On CPU bringup when cr4_set_bits_and_update_boot is called > mmu_cr4_features will now be written to. For the boot CPU, the > __ro_after_init on mmu_cr4_features does not cause a fault. However, > __ro_after_init was removed due to it triggering faults on non-boot > CPUs Before this patch, cr4_set_bits_and_update_boot() was only ever called during init. But, after this patch, it gets called later in boot and causes problems. We're surely not making _real_ updates to it, right? In that case the writes are superfluous and we would be better off just not writing to it (and retaining __ro_after_init) rather than allowing superfluous writes.