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[23.128.96.18]) by mx.google.com with ESMTP id y14si2352964edo.315.2020.06.18.11.23.28; Thu, 18 Jun 2020 11:23:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731263AbgFROve (ORCPT + 99 others); Thu, 18 Jun 2020 10:51:34 -0400 Received: from mga01.intel.com ([192.55.52.88]:45806 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731167AbgFROvc (ORCPT ); Thu, 18 Jun 2020 10:51:32 -0400 IronPort-SDR: +ta8xaTHcE4av6OKCeAmV2OapdGU75SHALJFiFJmmiHm3iFNUkG+D6zE+6MpecPi01dLIi72LN soFqa5By9rKg== X-IronPort-AV: E=McAfee;i="6000,8403,9655"; a="160692239" X-IronPort-AV: E=Sophos;i="5.75,251,1589266800"; d="scan'208";a="160692239" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2020 07:51:16 -0700 IronPort-SDR: dO6AxF1y1cue5QV4nymJ0uWPGEs0nyFjFXHsHvaW0nkWys+iOMeUQXJrBUjzLn9mrlk9W7e/+l 06Mfn4RWrhEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,526,1589266800"; d="scan'208";a="277645745" Received: from mcrum-mobl1.amr.corp.intel.com (HELO [10.255.0.127]) ([10.255.0.127]) by orsmga006.jf.intel.com with ESMTP; 18 Jun 2020 07:51:10 -0700 Subject: Re: [PATCH 2/4] KVM: x86: Introduce paravirt feature CR0/CR4 pinning To: "Andersen, John" Cc: corbet@lwn.net, pbonzini@redhat.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com, shuah@kernel.org, sean.j.christopherson@intel.com, liran.alon@oracle.com, drjones@redhat.com, rick.p.edgecombe@intel.com, kristen@linux.intel.com, vkuznets@redhat.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, mchehab+huawei@kernel.org, gregkh@linuxfoundation.org, paulmck@kernel.org, pawan.kumar.gupta@linux.intel.com, jgross@suse.com, mike.kravetz@oracle.com, oneukum@suse.com, luto@kernel.org, peterz@infradead.org, fenghua.yu@intel.com, reinette.chatre@intel.com, vineela.tummalapalli@intel.com, dave.hansen@linux.intel.com, arjan@linux.intel.com, caoj.fnst@cn.fujitsu.com, bhe@redhat.com, nivedita@alum.mit.edu, keescook@chromium.org, dan.j.williams@intel.com, eric.auger@redhat.com, aaronlewis@google.com, peterx@redhat.com, makarandsonare@google.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, kernel-hardening@lists.openwall.com References: <20200617190757.27081-1-john.s.andersen@intel.com> <20200617190757.27081-3-john.s.andersen@intel.com> <0fa9682e-59d4-75f7-366f-103d6b8e71b8@intel.com> <20200618144314.GB23@258ff54ff3c0> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200618144314.GB23@258ff54ff3c0> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/18/20 7:43 AM, Andersen, John wrote: > On Thu, Jun 18, 2020 at 07:18:09AM -0700, Dave Hansen wrote: >> On 6/17/20 12:07 PM, John Andersen wrote: >>> +#define KVM_CR0_PIN_ALLOWED (X86_CR0_WP) >>> +#define KVM_CR4_PIN_ALLOWED (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP) >> >> Why *is* there an allowed set? Why don't we just allow everything? >> >> Shouldn't we also pin any unknown bits? The CR4.FSGSBASE bit is an >> example of something that showed up CPUs without Linux knowing about it. >> If set, it causes problems. This set couldn't have helped FSGSBASE >> because it is not in the allowed set. >> >> Let's say Intel loses its marbles and adds a CR4 bit that lets userspace >> write to kernel memory. Linux won't set it, but an attacker would go >> after it, first thing. > > The allowed set came about because there were comments from internal review > where it was said that allowing the guest to pin TS and MP adds unnecessary > complexity. That would have been a great design point to include in the changelog. Could you make sure it shows up in future versions. > Also because KVM always intercepts these bits via the CR0/4_GUEST_HOST_MASK. If > we allow setting of any bits, then we have to add some infrastructure for > modifying the mask when pinned bits are updated. I have a patch for that if we > want to go that route, but it doesn't account for the added complexity > mentioned above. Well, we have a current, known issue (FSGSBASE) which shows how dealing with guest-unknown bits is required. To me, that overrules complexity arguments to a large degree.