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Thu, 18 Jun 2020 11:46:14 +0000 From: "Liu, Yi L" To: Jean-Philippe Brucker CC: "alex.williamson@redhat.com" , "eric.auger@redhat.com" , "baolu.lu@linux.intel.com" , "joro@8bytes.org" , "Tian, Kevin" , "jacob.jun.pan@linux.intel.com" , "Raj, Ashok" , "Tian, Jun J" , "Sun, Yi Y" , "peterx@redhat.com" , "Wu, Hao" , "iommu@lists.linux-foundation.org" , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "will@kernel.org" , "robin.murphy@arm.com" Subject: RE: [PATCH v2 02/15] iommu: Report domain nesting info Thread-Topic: [PATCH v2 02/15] iommu: Report domain nesting info Thread-Index: AQHWP+lAvgybSaO2NECN4P16s7e2zKjc6kyAgAFaSXA= Date: Thu, 18 Jun 2020 11:46:14 +0000 Message-ID: References: <1591877734-66527-1-git-send-email-yi.l.liu@intel.com> <1591877734-66527-3-git-send-email-yi.l.liu@intel.com> <20200617143909.GA886590@myrica> In-Reply-To: <20200617143909.GA886590@myrica> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.2.0.6 dlp-product: dlpe-windows authentication-results: linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.198.147.217] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f0d44784-4e10-4ec2-7294-08d8137d34ac x-ms-traffictypediagnostic: DM5PR1101MB2108: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; x-forefront-prvs: 0438F90F17 x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: KtsLESTArB/qOy0K5OMCWSdlXSlrPsUyKXOtmeBmYN3RBqOBGrLUxLmLLr0aeLXwf5gaD54GYOrPrdj4P1IhEXQEcOD/JtyRccmHcOpBRhJ1+1s6/keNQrO6AIYbkhnDOQbIRrKYT8aYmgRoWjZjMGbkxCDOd6T6pKQp0s/LyiCn5vMu/31OAd9U8RLxmAexFA3MQKy0B5PhLDExTJe+SCPCxF9ypV1jZJTVTqFly49Shqg6mcgBDDyNA6R9Xb/2J2Ajorb4GgDGk23/84Xdbh1G3fhpSnuspLlDwUttygNJyLiOKrSCBdE9B7lek2ZK90Qmg5lUVuJXqhe1dxQu5A== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM5PR11MB1435.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(4636009)(346002)(376002)(136003)(39860400002)(396003)(366004)(5660300002)(52536014)(6506007)(478600001)(86362001)(8936002)(4326008)(186003)(26005)(71200400001)(83380400001)(7696005)(33656002)(7416002)(54906003)(316002)(2906002)(55016002)(6916009)(9686003)(66476007)(66556008)(64756008)(66446008)(76116006)(66946007)(8676002);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata: 3YLUHKosrlkGtpx5GI5Yk3CSTowreJFJGNbAAfN1rVMaAIX6Y/wd0mlVHaQWnLS+HY89tFzxaMYcmgPMJEtpahNa2P7hQDcjtF68LEasbX20o4rs2XMANlk0mK1n/rO/dI7JgMSg3lXYjIss2pNVOJBxZh3urQXMO/4rS1CHoYG3+9bSzmt+mUs3TCb+qLa9erY0NFTFcfDZXNU6x05jPf3N0sKCduBh/i0eaznRfBHfh5B8CVlfwPSw1SGQzS5e79Zdd43ed/ELVqQCy1+VuNn15Hf+YoiI8lZT8zw35T+p9zB64JUo/hNncW3+ycGtzruxdj/+9nzXR/zDxQPoVMqdynakwgw9ifXbXE3WMzdvhbrVRal9f2cg4ETGX62vch8XfUMt0gpBHWuS7kmugh5ADY+yWvuuB60zEJdvGmJSGX/NIlhtvFBA99lpxltqLcW+BDJatWtimKRwXO/v8F6qQyWWrvOSpASwiLx9ZqQtLeGL0dtVbuBSrIwB3Iib Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: f0d44784-4e10-4ec2-7294-08d8137d34ac X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Jun 2020 11:46:14.5852 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 9BUmJTMLylUgoozkzduI8YivJzT2ev7eVNDBRBkrD4YA1Xt/2BwytlVSlqNKrigGWFrQchPBj/I0BOIAbNwvbw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1101MB2108 X-OriginatorOrg: intel.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jean, > From: Jean-Philippe Brucker < jean-philippe@linaro.org> > Sent: Wednesday, June 17, 2020 10:39 PM >=20 > [+ Will and Robin] >=20 > Hi Yi, >=20 > On Thu, Jun 11, 2020 at 05:15:21AM -0700, Liu Yi L wrote: > > IOMMUs that support nesting translation needs report the capability > > info to userspace, e.g. the format of first level/stage paging structur= es. > > > > Cc: Kevin Tian > > CC: Jacob Pan > > Cc: Alex Williamson > > Cc: Eric Auger > > Cc: Jean-Philippe Brucker > > Cc: Joerg Roedel > > Cc: Lu Baolu > > Signed-off-by: Liu Yi L > > Signed-off-by: Jacob Pan > > --- > > @Jean, Eric: as nesting was introduced for ARM, but looks like no > > actual user of it. right? So I'm wondering if we can reuse > > DOMAIN_ATTR_NESTING to retrieve nesting info? how about your opinions? >=20 > Sure, I think we could rework the getters for DOMAIN_ATTR_NESTING since t= hey > aren't used, but we do need to keep the setters as is. >=20 > Before attaching a domain, VFIO sets DOMAIN_ATTR_NESTING if userspace > requested a VFIO_TYPE1_NESTING_IOMMU container. This is necessary for the > SMMU driver to know how to attach later, but at that point we don't know = whether > the SMMU does support nesting (since the domain isn't attached to any end= point). > During attach, the SMMU driver adapts to the SMMU's capabilities, and may= well > fallback to one stage if the SMMU doesn't support nesting. got you. so even VFIO sets DOMAIN_ATTR_NESTING successfully, it doesn't mea= n the nesting will be used. yeah, it's a little bit different with VT-d side.= intel iommu driver will fail ATT_NESTING setting if it found not all iommu units in the= system are nesting capable. > VFIO should check after attaching that the nesting attribute held, by cal= ling > iommu_domain_get_attr(NESTING). At the moment it does not, and since your > 03/15 patch does that with additional info, I agree with reusing > DOMAIN_ATTR_NESTING instead of adding DOMAIN_ATTR_NESTING_INFO. > > However it requires changing the get_attr(NESTING) implementations in bot= h SMMU > drivers as a precursor of this series, to avoid breaking > VFIO_TYPE1_NESTING_IOMMU on Arm. Since we haven't yet defined the > nesting_info structs for SMMUv2 and v3, I suppose we could return an empt= y struct > iommu_nesting_info for now? got you. I think it works. So far, I didn't see any getter for ATTR_NESTING= , once SMMU drivers return empty struct iommu_nesting_info, VFIO won't fail. will do it when switching to reuse ATTR_NESTING for getting nesting info. > > > > include/linux/iommu.h | 1 + > > include/uapi/linux/iommu.h | 34 ++++++++++++++++++++++++++++++++++ > > 2 files changed, 35 insertions(+) > > > > diff --git a/include/linux/iommu.h b/include/linux/iommu.h index > > 78a26ae..f6e4b49 100644 > > --- a/include/linux/iommu.h > > +++ b/include/linux/iommu.h > > @@ -126,6 +126,7 @@ enum iommu_attr { > > DOMAIN_ATTR_FSL_PAMUV1, > > DOMAIN_ATTR_NESTING, /* two stages of translation */ > > DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, > > + DOMAIN_ATTR_NESTING_INFO, > > DOMAIN_ATTR_MAX, > > }; > > > > diff --git a/include/uapi/linux/iommu.h b/include/uapi/linux/iommu.h > > index 303f148..02eac73 100644 > > --- a/include/uapi/linux/iommu.h > > +++ b/include/uapi/linux/iommu.h > > @@ -332,4 +332,38 @@ struct iommu_gpasid_bind_data { > > }; > > }; > > > > +struct iommu_nesting_info { > > + __u32 size; > > + __u32 format; >=20 > What goes into format? And flags? This structure needs some documentation= . format will be the same with the definition of @format in iommu_gpasid_bind= _data. flags is reserved for future extension. will add description in next versio= n. :-) struct iommu_gpasid_bind_data { __u32 argsz; #define IOMMU_GPASID_BIND_VERSION_1 1 __u32 version; #define IOMMU_PASID_FORMAT_INTEL_VTD 1 __u32 format; #define IOMMU_SVA_GPASID_VAL (1 << 0) /* guest PASID valid */ __u64 flags; __u64 gpgd; __u64 hpasid; __u64 gpasid; __u32 addr_width; __u8 padding[12]; /* Vendor specific data */ union { struct iommu_gpasid_bind_data_vtd vtd; } vendor; }; Regards, Yi Liu > Thanks, > Jean >=20 > > + __u32 features; > > +#define IOMMU_NESTING_FEAT_SYSWIDE_PASID (1 << 0) > > +#define IOMMU_NESTING_FEAT_BIND_PGTBL (1 << 1) > > +#define IOMMU_NESTING_FEAT_CACHE_INVLD (1 << 2) > > + __u32 flags; > > + __u8 data[]; > > +}; > > + > > +/* > > + * @flags: VT-d specific flags. Currently reserved for future > > + * extension. > > + * @addr_width: The output addr width of first level/stage translation > > + * @pasid_bits: Maximum supported PASID bits, 0 represents no PASID > > + * support. > > + * @cap_reg: Describe basic capabilities as defined in VT-d capability > > + * register. > > + * @cap_mask: Mark valid capability bits in @cap_reg. > > + * @ecap_reg: Describe the extended capabilities as defined in VT-d > > + * extended capability register. > > + * @ecap_mask: Mark the valid capability bits in @ecap_reg. > > + */ > > +struct iommu_nesting_info_vtd { > > + __u32 flags; > > + __u16 addr_width; > > + __u16 pasid_bits; > > + __u64 cap_reg; > > + __u64 cap_mask; > > + __u64 ecap_reg; > > + __u64 ecap_mask; > > +}; > > + > > #endif /* _UAPI_IOMMU_H */ > > -- > > 2.7.4 > >