Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp2555791ybt; Mon, 22 Jun 2020 01:04:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzpvsU6fpqL7Fr/8r2t4sah2GIpztIncqDFrcPHqukvfwceggUq9ELeidXB+3Ajvtp7Jk5M X-Received: by 2002:a17:906:ced0:: with SMTP id si16mr14061362ejb.545.1592813064303; Mon, 22 Jun 2020 01:04:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592813064; cv=none; d=google.com; s=arc-20160816; b=yjGri8V48OSaAnWVWpsN9rD+GmyOwKBuct9PUy7oYkCdJxNPTiN6cuEyjPly1hrqYA 1TDl1PvI2dZRxX6TmjGx7aNtaDbjV7qgIJ3GAmNJV+uYm/n6Tj6LFJDTlgJrs28N4gC8 4R6YbbX1MVNjDqrCn9wSLbwI/sM1BQjd7IKVXEckyjzUVFayzRlAMBeQUyB/VdiyS+m6 sEpUQTJJNRzqBAyEKv2r6IfNe1MCqW1Z6tBHN0GArNVgJ9KFs5ltSNNyoVMqDFPOM2Og pJ4mbOM9S9JZ4P5iT7AUlcpOHOjskwfiSe7wbcZgVPzT18fjaxdsgDjmRlrlX+O9XUnN K7qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wsD4JPbpu6P4JVf54PUOXffj8NM5iwWqNtOuxNrh1Ek=; b=lJsX+nMGeTGdaKNVDrDb9TH3vdVsRotZuGnz9XK6phlCibiGTX+WaVn6pogZ/qeca8 2PL8VuoWwdZrzhFzNKcybVQ7dQwpTla/kc8vY7NtmfdXJgwyaOmt2OhW1owPBFimzh7R b+psldtVLZN9LAMMkVm4AGGJA5vh3tuaPt8jsFutq0vV/rVv+33kFvzikumoW6C39V/0 rrGVcURoWdclpqzUNJ2KYQK4tanqIpOqBTpYXYdnCt5nnXky8rD+/VloBnERBk3f+Fwi uVzIN+jRS78/cCqKQuPbmm8deEFpJHbMRVZx0nqBx/b7dX+E1DvqKgrGG+rapsmJy2dk I++Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BNOYV4j6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c6si8696868edw.220.2020.06.22.01.04.01; Mon, 22 Jun 2020 01:04:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BNOYV4j6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727968AbgFVH7z (ORCPT + 99 others); Mon, 22 Jun 2020 03:59:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726279AbgFVH7u (ORCPT ); Mon, 22 Jun 2020 03:59:50 -0400 Received: from mail-oi1-x243.google.com (mail-oi1-x243.google.com [IPv6:2607:f8b0:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E67DC061794 for ; Mon, 22 Jun 2020 00:59:50 -0700 (PDT) Received: by mail-oi1-x243.google.com with SMTP id t25so14817283oij.7 for ; Mon, 22 Jun 2020 00:59:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wsD4JPbpu6P4JVf54PUOXffj8NM5iwWqNtOuxNrh1Ek=; b=BNOYV4j6OzxYc7GgjKpKV5iHhJDTcp7c44mazYdUT13aaDi4kX/kj0nSDBVIy20Kuv 2iWXqdC8MelZ6pT8J7IMyiTr761V9lDjt40hGEj2cUegqHluLTKhW9JO/foBnKb8WbU2 FPTMALkLdzsxrhvNkF75jEIkblhVdLIjoKKaSmvy8I+JxtUpLFNkM/wPUoR+TPwKdnme MFx5YdfH7JjV73EMfUZOh8BCsp3DazzPy3yLz5VRQ2duLgqhUuGVSDFz3I1ctv8fCfH2 M8WPY5rpRck6TXr/33Onpu5U2a2hN/c5h6xux7gLdrFN5AN/3yTOAozV3wy6bYlLkajy jIcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wsD4JPbpu6P4JVf54PUOXffj8NM5iwWqNtOuxNrh1Ek=; b=NJBesOGbAuoYdSGP6oUGo01HD5WEpx7gZlKdo4Ur5qjMAywDiD/5QzwdqRa4uCchL2 RKliOTpjhU6o6kW9d7sWKjsNpC4oCN2TP8GNQLwK1NTrJ7+SVSUffrE97yiEqcMJE2OP zPIbpMbNfxxaVl9D4DYrG2mFC7wGjEKvt31IlA5XNz4n7OsNRGOyKeSy+1zdCXPl0fDM 3BnymmTXlj0wKmYatJ4QRVr40hq6eSFOC82xNtGJUmeUZH++pL9mrVoMsjbBW67bsT6b 4d1l7EAtgrK3V5Hz31WsSXEoaspNYHaL40UZoojtvQ4MAjZbtVt1jXJ40rfZpI8WMBOh r8+A== X-Gm-Message-State: AOAM533UGgAZIyoJsXfAP6oNHqt8u1Ku9PkkOyU7mo+FptRVtJ1sZn45 EE9py5bekQM424PsGRpvu2DEeQ== X-Received: by 2002:a05:6808:6ca:: with SMTP id m10mr11477202oih.27.1592812789939; Mon, 22 Jun 2020 00:59:49 -0700 (PDT) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id f7sm3135396otl.60.2020.06.22.00.59.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2020 00:59:49 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Ohad Ben-Cohen , Baolin Wang , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v2 3/4] hwspinlock: qcom: Allow mmio usage in addition to syscon Date: Mon, 22 Jun 2020 00:59:55 -0700 Message-Id: <20200622075956.171058-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200622075956.171058-1-bjorn.andersson@linaro.org> References: <20200622075956.171058-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In modern Qualcomm platforms the mutex region of the TCSR is forked off into its own block, all with a offset of 0 and stride of 4096, and in some of these platforms no other registers in this region is accessed from Linux. So add support for directly memory mapping this register space, to avoid the need to represent this block using a syscon. Reviewed-by: Baolin Wang Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson --- Changes since v1: - Use devm_platform_ioremap_resource() drivers/hwspinlock/qcom_hwspinlock.c | 70 +++++++++++++++++++++------- 1 file changed, 54 insertions(+), 16 deletions(-) diff --git a/drivers/hwspinlock/qcom_hwspinlock.c b/drivers/hwspinlock/qcom_hwspinlock.c index f0da544b14d2..364710966665 100644 --- a/drivers/hwspinlock/qcom_hwspinlock.c +++ b/drivers/hwspinlock/qcom_hwspinlock.c @@ -70,41 +70,79 @@ static const struct of_device_id qcom_hwspinlock_of_match[] = { }; MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match); -static int qcom_hwspinlock_probe(struct platform_device *pdev) +static struct regmap *qcom_hwspinlock_probe_syscon(struct platform_device *pdev, + u32 *base, u32 *stride) { - struct hwspinlock_device *bank; struct device_node *syscon; - struct reg_field field; struct regmap *regmap; - size_t array_size; - u32 stride; - u32 base; int ret; - int i; syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0); - if (!syscon) { - dev_err(&pdev->dev, "no syscon property\n"); - return -ENODEV; - } + if (!syscon) + return ERR_PTR(-ENODEV); regmap = syscon_node_to_regmap(syscon); of_node_put(syscon); if (IS_ERR(regmap)) - return PTR_ERR(regmap); + return regmap; - ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, &base); + ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, base); if (ret < 0) { dev_err(&pdev->dev, "no offset in syscon\n"); - return -EINVAL; + return ERR_PTR(-EINVAL); } - ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, &stride); + ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, stride); if (ret < 0) { dev_err(&pdev->dev, "no stride syscon\n"); - return -EINVAL; + return ERR_PTR(-EINVAL); } + return regmap; +} + +static const struct regmap_config tcsr_mutex_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40000, + .fast_io = true, +}; + +static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev, + u32 *offset, u32 *stride) +{ + struct device *dev = &pdev->dev; + void __iomem *base; + + /* All modern platform has offset 0 and stride of 4k */ + *offset = 0; + *stride = 0x1000; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return ERR_CAST(base); + + return devm_regmap_init_mmio(dev, base, &tcsr_mutex_config); +} + +static int qcom_hwspinlock_probe(struct platform_device *pdev) +{ + struct hwspinlock_device *bank; + struct reg_field field; + struct regmap *regmap; + size_t array_size; + u32 stride; + u32 base; + int i; + + regmap = qcom_hwspinlock_probe_syscon(pdev, &base, &stride); + if (IS_ERR(regmap) && PTR_ERR(regmap) == -ENODEV) + regmap = qcom_hwspinlock_probe_mmio(pdev, &base, &stride); + + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + array_size = QCOM_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock); bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL); if (!bank) -- 2.26.2