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[23.128.96.18]) by mx.google.com with ESMTP id op23si560795ejb.694.2020.06.22.01.44.34; Mon, 22 Jun 2020 01:44:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iEGUuJhL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726874AbgFVIk0 (ORCPT + 99 others); Mon, 22 Jun 2020 04:40:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726854AbgFVIkZ (ORCPT ); Mon, 22 Jun 2020 04:40:25 -0400 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A00B6C061796 for ; Mon, 22 Jun 2020 01:40:24 -0700 (PDT) Received: by mail-lj1-x242.google.com with SMTP id x18so18287688lji.1 for ; Mon, 22 Jun 2020 01:40:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=hFeVIaukde5cEJYosI/nKt2dPH3w8UvOLbWUnlXHsBU=; b=iEGUuJhLh3+NwbCNxjkkRe9EVuTa6QWYy1pemvrk9YZZt2QLagctJEfbVbcJm3GNqL XdU1vFbZpQJ9MY0yMrL+JM4jrBltzKfZAMow7TO4U8iz6WgaI8qShnkMrXigDZZFvxFD RBeIyRDTs+ycv/eO6kZtT1jPgvH7GJzZTAARh2+PpD0kHr0BSQrlEMwIN/jE38mW6Pmo YWEGWjwW5DsbhEW7jBaTCQuGWx+25ofFPoeJ2n7vJPcWvNpCNABDJHi4v2Mken1RB6r6 C9kML6zezbYAd/Hnqn1IPXNudHg0e+N4TYUl/2iU8PsJJWpYOTULbYAMymthaJOFfY7R idaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=hFeVIaukde5cEJYosI/nKt2dPH3w8UvOLbWUnlXHsBU=; b=nsrSdAlW/a6kO+li1a2fj30MN/ZARPH5X+jNL2wm1pFuazG3AXo/0Ziidggm+os/hs 91kgRq/XTTTNOFCeuFW/WD/7CGzsQ0ky0CfrJuLkb9O5AC7uQh1sP+T7BELRW6jlVDfq zA7WipDuZpjI075mm5cE5EvMdteRb4GIkAKfHCiEF5M27xajkNHew94FWwJxAY7fbhX/ 1UrZhA5Ov6LbvdQw+qBf7W1RFQO0idH2fv74+OK0x+D6BX7EDEhZDtosyj9gwz4yLF7X zF7Rz/HJVbGQ4rhpSl1hNoxB5R5xWJs5T5STQFI9App8H5lfIphlwMaqhjcA675nrMEH c+WA== X-Gm-Message-State: AOAM532WwKflVOHYByW6PFvpB1BchNSdtTuRdm0hrigj+npgiOQM9O4I 8R02dtSHfhN124NHgwyxeSfePQfgS6P6ha1U1af+Ow== X-Received: by 2002:a2e:9786:: with SMTP id y6mr7668442lji.398.1592815222900; Mon, 22 Jun 2020 01:40:22 -0700 (PDT) MIME-Version: 1.0 References: <20200621071841.GF128451@builder.lan> In-Reply-To: <20200621071841.GF128451@builder.lan> From: Amit Kucheria Date: Mon, 22 Jun 2020 14:10:11 +0530 Message-ID: Subject: Re: [PATCH 3/3] arm64: dts: qcom: sm8250: Add thermal zones and throttling support To: Bjorn Andersson Cc: Linux Kernel Mailing List , linux-arm-msm , Sibi Sankar , Manivannan Sadhasivam , Dmitry Baryshkov , Andy Gross , Daniel Lezcano , Zhang Rui , Amit Kucheria , DTML , Linux PM list Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Jun 21, 2020 at 12:51 PM Bjorn Andersson wrote: > > On Mon 08 Jun 23:44 PDT 2020, Amit Kucheria wrote: > > > sm8250 has 24 thermal sensors split across two tsens controllers. Add > > the thermal zones to expose them and wireup the cpus to throttle on > > crossing passive temperature thresholds. > > > > Update the comment in the drivers to list the SoCs it supports. > > > > Signed-off-by: Amit Kucheria > > --- > > arch/arm64/boot/dts/qcom/sm8250.dtsi | 766 +++++++++++++++++++++++++++ > > drivers/thermal/qcom/tsens-v2.c | 2 +- > > 2 files changed, 767 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > > index deaa8415c7b72..5cd18cd8a675b 100644 > > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > > @@ -8,6 +8,7 @@ > > #include > > #include > > #include > > +#include > > > > / { > > interrupt-parent = <&intc>; > > @@ -86,6 +87,7 @@ CPU0: cpu@0 { > > enable-method = "psci"; > > next-level-cache = <&L2_0>; > > qcom,freq-domain = <&cpufreq_hw 0>; > > + #cooling-cells = <2>; > > This doesn't apply to linux-next. > > The problem seems to be that, as pointed out when I submitted that > patch, the previously anonymous "cpufreq hardware" is now replaced by > the "EPSS" hardware block. I'll take a look. > So we need a new driver (or update the existing one) to support this new > hardware block. > > Presumably though, without this there's not much cooling anyways - which > is sad, as your patch looks good. > > > L2_0: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > [..] > > diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c > > index b293ed32174b5..58cac8f2a358c 100644 > > --- a/drivers/thermal/qcom/tsens-v2.c > > +++ b/drivers/thermal/qcom/tsens-v2.c > > @@ -26,7 +26,7 @@ > > #define TM_TRDY_OFF 0x00e4 > > #define TM_WDOG_LOG_OFF 0x013c > > > > -/* v2.x: 8996, 8998, sdm845 */ > > +/* v2.x: 8996, 8998, sc7180, sdm845, sm8150, sm8250 */ > > Even though it's trivial, can you please send this through the tsens > tree instead, so we don't end up having unnecessary merge conflicts. > Will do. Thanks for the review.