Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp3742186ybt; Tue, 23 Jun 2020 09:36:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxFpCaU2iR0/n+C1be8k3TpSShZjuINF0k7d85YwRGWZyKo5UiJvaAq61ig4egUbDmE/K85 X-Received: by 2002:a17:906:82d2:: with SMTP id a18mr140215ejy.522.1592930182308; Tue, 23 Jun 2020 09:36:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592930182; cv=none; d=google.com; s=arc-20160816; b=b7VRvlCaTZB37eGHo98JpFHCwOTYDu4q7/024EDY0OKfR0VStKb9qJhu/4MarA+3Mx Ttk8Ez6yPtNMW9EVnVAdbKra1hT+eWQbebGu57FJPIH5BhIop075mqvi3g4KXeF7iAxO fJt2538zinW0guxV7Si7rqqCVp2xkOhTPmPWfnTy7mJ00C84joVzknx1f1psjLVG0JaC cEVP37ORcLwdvwYIu5VWNLXj2nLBTZsf7B3wl/pd8qZ1HN0gAw8A9sEfyTnEwzcacUu0 fw9Fx5sammrHILNgVGBkp/ZYEtSx0TcfUH5Z+BDSvXuYbUicH23A7ZJcFY38SWkuOpLV g2Mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=qpEvjv/v6DnXapTFU/B8CIvtd8hdeFxcDqsJe5tUyKI=; b=zZ1NqZlXqMCDiErTFfIsDuiIsuZIS7x55GOUzmax7y/7iRf266XTx96s3JGje1S01W l03IgelYqPQhPUwjK44/Yqhz73fkpZY+akukBHx6KkQcNeSLZwjRKcyVDR131RH3JpBx ulEN21LvuNRM7Y/sZTwzbWRro7IdZDDBadcug4OyLEVxjTTVhtnkxYvyK9ny2qaa9+u0 gg29Tak7uTDdKqcPBeyGnXCW+HOS9R+QunGxxDiSvhGTn4Lk6+bQyJEjTVg7LHpA4m9C BtlgFqRZyZRpopJKLEcQ+jW5e5z8k+RUEiR+j2U1pZZXl1wrWkspi2knAZoYUDsUQf3a xzCw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id cy17si2695463edb.152.2020.06.23.09.35.58; Tue, 23 Jun 2020 09:36:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732532AbgFWQfv (ORCPT + 99 others); Tue, 23 Jun 2020 12:35:51 -0400 Received: from cloudserver094114.home.pl ([79.96.170.134]:43978 "EHLO cloudserver094114.home.pl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729481AbgFWQfu (ORCPT ); Tue, 23 Jun 2020 12:35:50 -0400 Received: from 89-64-86-94.dynamic.chello.pl (89.64.86.94) (HELO kreacher.localnet) by serwer1319399.home.pl (79.96.170.134) with SMTP (IdeaSmtpServer 0.83.415) id cfb7520a50996e14; Tue, 23 Jun 2020 18:35:48 +0200 From: "Rafael J. Wysocki" To: Srinivas Pandruvada Cc: lenb@kernel.org, viresh.kumar@linaro.org, dsmythies@telus.net, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] cpufreq: intel_pstate: Add additional OOB enabling bit Date: Tue, 23 Jun 2020 18:35:48 +0200 Message-ID: <1776411.KcV3dxTrbR@kreacher> In-Reply-To: <20200612180957.1018235-1-srinivas.pandruvada@linux.intel.com> References: <20200612180957.1018235-1-srinivas.pandruvada@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Friday, June 12, 2020 8:09:57 PM CEST Srinivas Pandruvada wrote: > Add additional bit for OOB (Out of band) enabling of P-states. In this > case intel_pstate shouldn't load. Currently, only "BIT(8) == 1" of the > MSR MSR_MISC_PWR_MGMT is considered as OOB. Also add "BIT(18) == 1" as > OOB condition. > > Signed-off-by: Srinivas Pandruvada > --- > v2 > - As suggested by Doug add OOB in debug message > - Atleast added local definition of OOB mask > > drivers/cpufreq/intel_pstate.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c > index 8e23a698ce04..4e9bfd2509b8 100644 > --- a/drivers/cpufreq/intel_pstate.c > +++ b/drivers/cpufreq/intel_pstate.c > @@ -2677,6 +2677,7 @@ static struct acpi_platform_list plat_info[] __initdata = { > { } /* End */ > }; > > +#define BITMASK_OOB (BIT(8) | BIT(18)) > static bool __init intel_pstate_platform_pwr_mgmt_exists(void) > { > const struct x86_cpu_id *id; > @@ -2686,8 +2687,9 @@ static bool __init intel_pstate_platform_pwr_mgmt_exists(void) > id = x86_match_cpu(intel_pstate_cpu_oob_ids); > if (id) { > rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); > - if (misc_pwr & (1 << 8)) { > - pr_debug("Bit 8 in the MISC_PWR_MGMT MSR set\n"); > + if (misc_pwr & BITMASK_OOB) { > + pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); > + pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); > return true; > } > } > Applied as 5.8-rc material with some edits in the subject/changelog, thanks!